Struct rp2040_pac::ppb::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub syst_csr: SYST_CSR,
    pub syst_rvr: SYST_RVR,
    pub syst_cvr: SYST_CVR,
    pub syst_calib: SYST_CALIB,
    pub nvic_iser: NVIC_ISER,
    pub nvic_icer: NVIC_ICER,
    pub nvic_ispr: NVIC_ISPR,
    pub nvic_icpr: NVIC_ICPR,
    pub nvic_ipr0: NVIC_IPR0,
    pub nvic_ipr1: NVIC_IPR1,
    pub nvic_ipr2: NVIC_IPR2,
    pub nvic_ipr3: NVIC_IPR3,
    pub nvic_ipr4: NVIC_IPR4,
    pub nvic_ipr5: NVIC_IPR5,
    pub nvic_ipr6: NVIC_IPR6,
    pub nvic_ipr7: NVIC_IPR7,
    pub cpuid: CPUID,
    pub icsr: ICSR,
    pub vtor: VTOR,
    pub aircr: AIRCR,
    pub scr: SCR,
    pub ccr: CCR,
    pub shpr2: SHPR2,
    pub shpr3: SHPR3,
    pub shcsr: SHCSR,
    pub mpu_type: MPU_TYPE,
    pub mpu_ctrl: MPU_CTRL,
    pub mpu_rnr: MPU_RNR,
    pub mpu_rbar: MPU_RBAR,
    pub mpu_rasr: MPU_RASR,
    // some fields omitted
}

Register block

Fields

syst_csr: SYST_CSR

0xe010 - Use the SysTick Control and Status Register to enable the SysTick features.

syst_rvr: SYST_RVR

0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.

syst_cvr: SYST_CVR

0xe018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.

syst_calib: SYST_CALIB

0xe01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

nvic_iser: NVIC_ISER

0xe100 - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

nvic_icer: NVIC_ICER

0xe180 - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.

nvic_ispr: NVIC_ISPR

0xe200 - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.

nvic_icpr: NVIC_ICPR

0xe280 - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.

nvic_ipr0: NVIC_IPR0

0xe400 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n These registers are only word-accessible

nvic_ipr1: NVIC_IPR1

0xe404 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr2: NVIC_IPR2

0xe408 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr3: NVIC_IPR3

0xe40c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr4: NVIC_IPR4

0xe410 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr5: NVIC_IPR5

0xe414 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr6: NVIC_IPR6

0xe418 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr7: NVIC_IPR7

0xe41c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

cpuid: CPUID

0xed00 - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.

icsr: ICSR

0xed04 - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.

vtor: VTOR

0xed08 - The VTOR holds the vector table offset address.

aircr: AIRCR

0xed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

scr: SCR

0xed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

ccr: CCR

0xed14 - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.

shpr2: SHPR2

0xed1c - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.

shpr3: SHPR3

0xed20 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.

shcsr: SHCSR

0xed24 - Use the System Handler Control and State Register to determine or clear the pending status of SVCall.

mpu_type: MPU_TYPE

0xed90 - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.

mpu_ctrl: MPU_CTRL

0xed94 - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.

mpu_rnr: MPU_RNR

0xed98 - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.

mpu_rbar: MPU_RBAR

0xed9c - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.

mpu_rasr: MPU_RASR

0xeda0 - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.