riscv2 0.1.2

#![allow(clippy::missing_safety_doc)]
//! Low level access to RISC-V processors
//!
//! # Features
//!
//! This crate provides:
//!
//! - Access to core registers like `mstatus` or `mcause`.
//! - Interrupt manipulation mechanisms.
//! - Wrappers around assembly instructions like `WFI`.

#![no_std]
#![feature(asm)]

pub mod asm;
pub mod interrupt;
pub mod register;