Crate riscv

Low level access to RISC-V processors

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.60 and up. It might compile with older versions but that may change in any new patch release.

Features

This crate provides:

• Access to core registers like mstatus or mcause.
• Interrupt manipulation mechanisms.
• Wrappers around assembly instructions like WFI.

Optional features

s-mode

This feature re-exports in interrupt S-mode interrupt functions defined in interrupt::supervisor. By default, the crate assumes that the target is running in M-mode. Thus, interrupt re-exports the M-mode functions defined in interrupt::machine.

critical-section-single-hart

This feature enables a critical-section implementation suitable for single-hart targets, based on disabling interrupts globally. This feature uses S-mode interrupt handling if the s-mode feature is enabled, and M-mode otherwise.

It is unsound to enable it on multi-hart targets, and may cause functional problems in systems where some interrupts must NOT be disabled or critical sections are managed as part of an RTOS. In these cases, you should use a target-specific implementation instead, typically provided by a HAL or RTOS crate.

Modules

• asm
  Assembly instructions
• delay
  Delay devices and providers
• interrupt
  Interrupts
• register
  RISC-V CSR’s

Macros

• singleton
  Macro to create a mutable reference to a statically allocated value