[−][src]Trait riscv_sandbox::machine::IntegerMachine

pub trait IntegerMachine {
    type IntegerType: MachineInteger;
    fn cycle(&mut self, _: &mut dyn Memory);

    fn get_i_register(&self, id: usize) -> Self::IntegerType;

    fn set_i_register(&mut self, id: usize, value: Self::IntegerType);

    fn get_pc(&self) -> Self::IntegerType;

    fn set_pc(&mut self, value: Self::IntegerType);

    fn get_csr_field(&self, id: CsrField) -> Self::IntegerType;

    fn set_csr_field(&mut self, id: CsrField, value: Self::IntegerType);

    fn get_privilege(&self) -> u8;

    fn set_privilege(&mut self, privilege: u8);

    fn finished(&self) -> bool;

    fn get_csr(&self, id: CsrId) -> Option<Self::IntegerType> { ... }

    fn set_csr(&mut self, id: CsrId, value: Self::IntegerType) -> Option<()> { ... }

    fn raise_exception(
        &mut self, 
        is_interrupt: bool, 
        code: i32, 
        info: Self::IntegerType, 
        pc: Self::IntegerType
    ) { ... }
}

This trait represent the minimal implementation of a RISC-V Machine. It needs to give access to integer registers and CSR registers.

Associated Types

type IntegerType: MachineInteger

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Required methods

fn cycle(&mut self, _: &mut dyn Memory)

A single clock cycle

fn get_i_register(&self, id: usize) -> Self::IntegerType

fn set_i_register(&mut self, id: usize, value: Self::IntegerType)

fn get_pc(&self) -> Self::IntegerType

As this function is the get counterpart of set_pc(), it needs to return the right PC (in pipelined simulators there are multiple "PCs"). This function returns the PC of the instruction we are fetching.

fn set_pc(&mut self, value: Self::IntegerType)

This function is crucial as it is used in helpers such as raise_exception(). It is used to set the PC of the fetched instruction. When calling cycle() the PC set by this function will be used to get the next instruction to be executed.

fn get_csr_field(&self, id: CsrField) -> Self::IntegerType

Gets a CSR Field's value. As CSR Fields are bit slices never wider than XLEN, we return an XLEN-wide number with bitN of the XLEN number corresponding to bitN of the CSR Field.

fn set_csr_field(&mut self, id: CsrField, value: Self::IntegerType)

Sets a CSR Field's value. As CSR Fields are bit slices never wider than XLEN, the parameter is a XLEN-wide number with bitN of the parameter corresponding to bitN of the CSR Field.

fn get_privilege(&self) -> u8

Gets privilege level of the processor. 0b00, 0b01, 0b11 correspond respectively to Machine, Supervisor, and User privilege.

fn set_privilege(&mut self, privilege: u8)

Sets privilege level of the processor. 0b00, 0b01, 0b11 correspond respectively to Machine, Supervisor, and User privilege.

fn finished(&self) -> bool

Tells if the machine has finished

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Provided methods

fn get_csr(&self, id: CsrId) -> Option<Self::IntegerType>

This function is a helper function to access CSR with CSRRx instructions. Many CSR fields are placed in the same CSR , but with different access privileges. The best example is mstatus CSR which contains many Machine-level fields, but also Supervisor-level fields which can be accessed with the sstatus CSR.

fn set_csr(&mut self, id: CsrId, value: Self::IntegerType) -> Option<()>

Setter for CSR registers. This function has a default definition using set_csr_field(). By default, we test for privilege level, access mode (WARL/WLRL/RO/RW), and we take care or setting bit fields at the right offset in the register.

fn raise_exception(
    &mut self,
    is_interrupt: bool,
    code: i32,
    info: Self::IntegerType,
    pc: Self::IntegerType
)

This function is the default implementation of the way an exception is raised in RISC-V. It only needs to have some CSR Fields implemented and a way to set the privilege level and the PC of the processor. This function is used whenever the processor implementation needs to raise an exception (e.g. missaligned or illegal instruction)

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Implementors

impl IntegerMachine for riscv_sandbox::machine::rv32imc::Machine[src]

type IntegerType = i32

impl IntegerMachine for riscv_sandbox::machine::rv32pthread::Machine[src]

type IntegerType = i32

impl IntegerMachine for riscv_sandbox::machine::simtx::Machine[src]

type IntegerType = i32

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