riscv-instructions 0.1.0

The table of RISC-V RV64GC (and Q, Zifencei, Zicsr) unprivileged instructions parsed from the official specification's TeX
Documentation
Copyright 2021 Jacob Lifshay

This file is part of RISC-V JIT Emulator.

RISC-V JIT Emulator is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 2.1 of the License, or
(at your option) any later version.

RISC-V JIT Emulator is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU Lesser General Public License for more details.

You should have received a copy of the GNU Lesser General Public License
along with RISC-V JIT Emulator.  If not, see <https://www.gnu.org/licenses/>.