Struct raw_cpuid::L1CacheTlbInfo[][src]

pub struct L1CacheTlbInfo { /* fields omitted */ }
Expand description

L1 Cache and TLB Information (LEAF=0x8000_0005).

Availability

✅ AMD ❌ Intel (reserved=0)

Implementations

Data TLB associativity for 2-MB and 4-MB pages.

Data TLB number of entries for 2-MB and 4-MB pages.

The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value.

Instruction TLB associativity for 2-MB and 4-MB pages.

Instruction TLB number of entries for 2-MB and 4-MB pages.

The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value.

Data TLB associativity for 4K pages.

Data TLB number of entries for 4K pages.

Instruction TLB associativity for 4K pages.

Instruction TLB number of entries for 4K pages.

L1 data cache size in KB

L1 data cache associativity.

L1 data cache lines per tag.

L1 data cache line size in bytes.

L1 instruction cache size in KB

L1 instruction cache associativity.

L1 instruction cache lines per tag.

L1 instruction cache line size in bytes.

Trait Implementations

Formats the value using the given formatter. Read more

This method tests for self and other values to be equal, and is used by ==. Read more

This method tests for !=.

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more

Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Performs the conversion.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.