Crate raw_cpuid[−][src]

Expand description

A library to parse the x86 CPUID instruction, written in rust with no external dependencies. The implementation closely resembles the Intel CPUID manual description. The library works with no_std.

Example

use raw_cpuid::CpuId;
let cpuid = CpuId::new();

if let Some(vf) = cpuid.get_vendor_info() {
    assert!(vf.as_string() == "GenuineIntel" || vf.as_string() == "AuthenticAMD");
}

let has_sse = cpuid.get_feature_info().map_or(false, |finfo| finfo.has_sse());
if has_sse {
    println!("CPU supports SSE!");
}

if let Some(cparams) = cpuid.get_cache_parameters() {
    for cache in cparams {
        let size = cache.associativity() * cache.physical_line_partitions() * cache.coherency_line_size() * cache.sets();
        println!("L{}-Cache size is {}", cache.level(), size);
    }
} else {
    println!("No cache parameter information available")
}

Platform support

CPU vendors may choose to not support certain functions/leafs in cpuid or only support them partially. We highlight this with the following emojis throughout the documentation:

✅: This struct/function is fully supported by the vendor.
🟡: This struct is partially supported by the vendor, refer to individual functions for more information.
❌: This struct/function is not supported by the vendor. When queried on this platform, we will return None/false/0 (or some other sane default).

Note that the presence of a ✅ does not guarantee that a specific feature will exist for your CPU – just that it is potentially supported by the vendor on some of its chips. You will still have to query it at runtime.

Modules

Uses Rust’s cpuid function from the arch module.

Macros

Macro which queries cpuid directly.

Structs

Processor Power Management and RAS Capabilities (LEAF=0x8000_0007).

Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).

Used to iterate over cache information contained in cpuid instruction.

CacheParametersIter

Main type used to query for information about the CPU we’re running on.

Low-level data-structure to store result of cpuid instruction.

Deterministic Address Translation Structure

Deterministic Address Translation Structure Iterator

DirectCacheAccessInfo

EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section

ExtendedFeatures

ExtendedFunctionInfo

ExtendedProcessorFeatureIdentifiers

Extended Processor and Processor Feature Identifiers (LEAF=0x8000_0001)

ExtendedStateInfo

ExtendedStateIter

ExtendedTopologyIter

Iterates over the system topology in order to retrieve more system information at each level of the topology.

ExtendedTopologyLevel

Gives detailed information about the current level in the topology (how many cores, what type etc.).

Information about Hypervisor

L1 Cache and TLB Information (LEAF=0x8000_0005).

L2And3CacheTlbInfo

L2/L3 Cache and TLB Information (LEAF=0x8000_0006).

L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 2).

L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 1).

L3MonitoringInfo

MemBwAllocationInfo

Memory Bandwidth Allocation Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 3).

MemoryEncryptionInfo

Encrypted Memory Capabilities

MonitorMwaitInfo

PerformanceMonitoringInfo

ProcessorBrandString

ASCII string up to 48 characters in length corresponding to the processor name. (LEAF = 0x8000_0002..=0x8000_0004)

ProcessorCapacityAndFeatureInfo

Processor Capacity Parameters and Extended Feature Identification (LEAF=0x8000_0008).

ProcessorFrequencyInfo

Processor Frequency Information

ProcessorSerial

ProcessorTraceInfo

RdtAllocationInfo

RdtMonitoringInfo

Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0 and ECX = 1)

Iterator over the SGX sub-leafs (ECX >= 2).

SoCVendorAttributesIter

ThermalPowerInfo

Time Stamp Counter and Nominal Core Crystal Clock Information Leaf.

Enums

What type of cache are we dealing with?

Deterministic Address Translation cache type (EDX bits 04 – 00)

Identifies the different Hypervisor products.

L2Associativity

Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)

What type of core we have at this level in the topology (real CPU or hyper-threaded).

Constants

CACHE_INFO_TABLE

This table is taken from Intel manual (Section CPUID instruction).