ra6m3/glcdc/
syscnt_inten.rs

1#[doc = "Register `SYSCNT_INTEN` reader"]
2pub struct R(crate::R<SYSCNT_INTEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYSCNT_INTEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYSCNT_INTEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYSCNT_INTEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYSCNT_INTEN` writer"]
17pub struct W(crate::W<SYSCNT_INTEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYSCNT_INTEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYSCNT_INTEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYSCNT_INTEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VPOSINTEN` reader - Interrupt request signal GLCDC_VPOS enable control."]
38pub type VPOSINTEN_R = crate::BitReader<VPOSINTEN_A>;
39#[doc = "Interrupt request signal GLCDC_VPOS enable control.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum VPOSINTEN_A {
42    #[doc = "1: Enables GLCDC_VPOS output"]
43    _1 = 1,
44    #[doc = "0: Disables GLCDC_VPOS output"]
45    _0 = 0,
46}
47impl From<VPOSINTEN_A> for bool {
48    #[inline(always)]
49    fn from(variant: VPOSINTEN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl VPOSINTEN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> VPOSINTEN_A {
57        match self.bits {
58            true => VPOSINTEN_A::_1,
59            false => VPOSINTEN_A::_0,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_1`"]
63    #[inline(always)]
64    pub fn is_1(&self) -> bool {
65        *self == VPOSINTEN_A::_1
66    }
67    #[doc = "Checks if the value of the field is `_0`"]
68    #[inline(always)]
69    pub fn is_0(&self) -> bool {
70        *self == VPOSINTEN_A::_0
71    }
72}
73#[doc = "Field `VPOSINTEN` writer - Interrupt request signal GLCDC_VPOS enable control."]
74pub type VPOSINTEN_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, SYSCNT_INTEN_SPEC, VPOSINTEN_A, O>;
76impl<'a, const O: u8> VPOSINTEN_W<'a, O> {
77    #[doc = "Enables GLCDC_VPOS output"]
78    #[inline(always)]
79    pub fn _1(self) -> &'a mut W {
80        self.variant(VPOSINTEN_A::_1)
81    }
82    #[doc = "Disables GLCDC_VPOS output"]
83    #[inline(always)]
84    pub fn _0(self) -> &'a mut W {
85        self.variant(VPOSINTEN_A::_0)
86    }
87}
88#[doc = "Field `L1UNDFINTEN` reader - Interrupt request signal GLCDC_L1UNDF enable control."]
89pub type L1UNDFINTEN_R = crate::BitReader<L1UNDFINTEN_A>;
90#[doc = "Interrupt request signal GLCDC_L1UNDF enable control.\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum L1UNDFINTEN_A {
93    #[doc = "1: Enables GLCDC_L1UNDF output"]
94    _1 = 1,
95    #[doc = "0: Disables GLCDC_L1UNDF output"]
96    _0 = 0,
97}
98impl From<L1UNDFINTEN_A> for bool {
99    #[inline(always)]
100    fn from(variant: L1UNDFINTEN_A) -> Self {
101        variant as u8 != 0
102    }
103}
104impl L1UNDFINTEN_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> L1UNDFINTEN_A {
108        match self.bits {
109            true => L1UNDFINTEN_A::_1,
110            false => L1UNDFINTEN_A::_0,
111        }
112    }
113    #[doc = "Checks if the value of the field is `_1`"]
114    #[inline(always)]
115    pub fn is_1(&self) -> bool {
116        *self == L1UNDFINTEN_A::_1
117    }
118    #[doc = "Checks if the value of the field is `_0`"]
119    #[inline(always)]
120    pub fn is_0(&self) -> bool {
121        *self == L1UNDFINTEN_A::_0
122    }
123}
124#[doc = "Field `L1UNDFINTEN` writer - Interrupt request signal GLCDC_L1UNDF enable control."]
125pub type L1UNDFINTEN_W<'a, const O: u8> =
126    crate::BitWriter<'a, u32, SYSCNT_INTEN_SPEC, L1UNDFINTEN_A, O>;
127impl<'a, const O: u8> L1UNDFINTEN_W<'a, O> {
128    #[doc = "Enables GLCDC_L1UNDF output"]
129    #[inline(always)]
130    pub fn _1(self) -> &'a mut W {
131        self.variant(L1UNDFINTEN_A::_1)
132    }
133    #[doc = "Disables GLCDC_L1UNDF output"]
134    #[inline(always)]
135    pub fn _0(self) -> &'a mut W {
136        self.variant(L1UNDFINTEN_A::_0)
137    }
138}
139#[doc = "Field `L2UNDFINTEN` reader - Interrupt request signal GLCDC_L2UNDF enable control."]
140pub type L2UNDFINTEN_R = crate::BitReader<L2UNDFINTEN_A>;
141#[doc = "Interrupt request signal GLCDC_L2UNDF enable control.\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum L2UNDFINTEN_A {
144    #[doc = "1: Enables GLCDC_L2UNDF output"]
145    _1 = 1,
146    #[doc = "0: Disables GLCDC_L2UNDF output"]
147    _0 = 0,
148}
149impl From<L2UNDFINTEN_A> for bool {
150    #[inline(always)]
151    fn from(variant: L2UNDFINTEN_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl L2UNDFINTEN_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> L2UNDFINTEN_A {
159        match self.bits {
160            true => L2UNDFINTEN_A::_1,
161            false => L2UNDFINTEN_A::_0,
162        }
163    }
164    #[doc = "Checks if the value of the field is `_1`"]
165    #[inline(always)]
166    pub fn is_1(&self) -> bool {
167        *self == L2UNDFINTEN_A::_1
168    }
169    #[doc = "Checks if the value of the field is `_0`"]
170    #[inline(always)]
171    pub fn is_0(&self) -> bool {
172        *self == L2UNDFINTEN_A::_0
173    }
174}
175#[doc = "Field `L2UNDFINTEN` writer - Interrupt request signal GLCDC_L2UNDF enable control."]
176pub type L2UNDFINTEN_W<'a, const O: u8> =
177    crate::BitWriter<'a, u32, SYSCNT_INTEN_SPEC, L2UNDFINTEN_A, O>;
178impl<'a, const O: u8> L2UNDFINTEN_W<'a, O> {
179    #[doc = "Enables GLCDC_L2UNDF output"]
180    #[inline(always)]
181    pub fn _1(self) -> &'a mut W {
182        self.variant(L2UNDFINTEN_A::_1)
183    }
184    #[doc = "Disables GLCDC_L2UNDF output"]
185    #[inline(always)]
186    pub fn _0(self) -> &'a mut W {
187        self.variant(L2UNDFINTEN_A::_0)
188    }
189}
190impl R {
191    #[doc = "Bit 0 - Interrupt request signal GLCDC_VPOS enable control."]
192    #[inline(always)]
193    pub fn vposinten(&self) -> VPOSINTEN_R {
194        VPOSINTEN_R::new((self.bits & 1) != 0)
195    }
196    #[doc = "Bit 1 - Interrupt request signal GLCDC_L1UNDF enable control."]
197    #[inline(always)]
198    pub fn l1undfinten(&self) -> L1UNDFINTEN_R {
199        L1UNDFINTEN_R::new(((self.bits >> 1) & 1) != 0)
200    }
201    #[doc = "Bit 2 - Interrupt request signal GLCDC_L2UNDF enable control."]
202    #[inline(always)]
203    pub fn l2undfinten(&self) -> L2UNDFINTEN_R {
204        L2UNDFINTEN_R::new(((self.bits >> 2) & 1) != 0)
205    }
206}
207impl W {
208    #[doc = "Bit 0 - Interrupt request signal GLCDC_VPOS enable control."]
209    #[inline(always)]
210    #[must_use]
211    pub fn vposinten(&mut self) -> VPOSINTEN_W<0> {
212        VPOSINTEN_W::new(self)
213    }
214    #[doc = "Bit 1 - Interrupt request signal GLCDC_L1UNDF enable control."]
215    #[inline(always)]
216    #[must_use]
217    pub fn l1undfinten(&mut self) -> L1UNDFINTEN_W<1> {
218        L1UNDFINTEN_W::new(self)
219    }
220    #[doc = "Bit 2 - Interrupt request signal GLCDC_L2UNDF enable control."]
221    #[inline(always)]
222    #[must_use]
223    pub fn l2undfinten(&mut self) -> L2UNDFINTEN_W<2> {
224        L2UNDFINTEN_W::new(self)
225    }
226    #[doc = "Writes raw bits to the register."]
227    #[inline(always)]
228    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
229        self.0.bits(bits);
230        self
231    }
232}
233#[doc = "System Control Block Interrupt Request Enable Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syscnt_inten](index.html) module"]
234pub struct SYSCNT_INTEN_SPEC;
235impl crate::RegisterSpec for SYSCNT_INTEN_SPEC {
236    type Ux = u32;
237}
238#[doc = "`read()` method returns [syscnt_inten::R](R) reader structure"]
239impl crate::Readable for SYSCNT_INTEN_SPEC {
240    type Reader = R;
241}
242#[doc = "`write(|w| ..)` method takes [syscnt_inten::W](W) writer structure"]
243impl crate::Writable for SYSCNT_INTEN_SPEC {
244    type Writer = W;
245    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
246    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
247}
248#[doc = "`reset()` method sets SYSCNT_INTEN to value 0"]
249impl crate::Resettable for SYSCNT_INTEN_SPEC {
250    const RESET_VALUE: Self::Ux = 0;
251}
ra6m3/glcdc/syscnt_inten.rs

ra6m3/glcdc/
syscnt_inten.rs
