ra4m2/sci0/
scmr.rs

1#[doc = "Register `SCMR` reader"]
2pub struct R(crate::R<SCMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCMR` writer"]
17pub struct W(crate::W<SCMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SMIF` reader - Smart Card Interface Mode Select"]
38pub type SMIF_R = crate::BitReader<SMIF_A>;
39#[doc = "Smart Card Interface Mode Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SMIF_A {
42    #[doc = "0: Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)"]
43    _0 = 0,
44    #[doc = "1: Smart card interface mode"]
45    _1 = 1,
46}
47impl From<SMIF_A> for bool {
48    #[inline(always)]
49    fn from(variant: SMIF_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SMIF_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SMIF_A {
57        match self.bits {
58            false => SMIF_A::_0,
59            true => SMIF_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == SMIF_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == SMIF_A::_1
71    }
72}
73#[doc = "Field `SMIF` writer - Smart Card Interface Mode Select"]
74pub type SMIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCMR_SPEC, SMIF_A, O>;
75impl<'a, const O: u8> SMIF_W<'a, O> {
76    #[doc = "Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(SMIF_A::_0)
80    }
81    #[doc = "Smart card interface mode"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(SMIF_A::_1)
85    }
86}
87#[doc = "Field `SINV` reader - Transmitted/Received Data Invert"]
88pub type SINV_R = crate::BitReader<SINV_A>;
89#[doc = "Transmitted/Received Data Invert\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum SINV_A {
92    #[doc = "0: TDR contents are transmitted as they are. Received data is stored as received in the RDR register."]
93    _0 = 0,
94    #[doc = "1: TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register."]
95    _1 = 1,
96}
97impl From<SINV_A> for bool {
98    #[inline(always)]
99    fn from(variant: SINV_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl SINV_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> SINV_A {
107        match self.bits {
108            false => SINV_A::_0,
109            true => SINV_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == SINV_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == SINV_A::_1
121    }
122}
123#[doc = "Field `SINV` writer - Transmitted/Received Data Invert"]
124pub type SINV_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCMR_SPEC, SINV_A, O>;
125impl<'a, const O: u8> SINV_W<'a, O> {
126    #[doc = "TDR contents are transmitted as they are. Received data is stored as received in the RDR register."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(SINV_A::_0)
130    }
131    #[doc = "TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(SINV_A::_1)
135    }
136}
137#[doc = "Field `SDIR` reader - Transmitted/Received Data Transfer Direction"]
138pub type SDIR_R = crate::BitReader<SDIR_A>;
139#[doc = "Transmitted/Received Data Transfer Direction\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum SDIR_A {
142    #[doc = "0: Transfer LSB-first"]
143    _0 = 0,
144    #[doc = "1: Transfer MSB-first"]
145    _1 = 1,
146}
147impl From<SDIR_A> for bool {
148    #[inline(always)]
149    fn from(variant: SDIR_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl SDIR_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> SDIR_A {
157        match self.bits {
158            false => SDIR_A::_0,
159            true => SDIR_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == SDIR_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == SDIR_A::_1
171    }
172}
173#[doc = "Field `SDIR` writer - Transmitted/Received Data Transfer Direction"]
174pub type SDIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCMR_SPEC, SDIR_A, O>;
175impl<'a, const O: u8> SDIR_W<'a, O> {
176    #[doc = "Transfer LSB-first"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(SDIR_A::_0)
180    }
181    #[doc = "Transfer MSB-first"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(SDIR_A::_1)
185    }
186}
187#[doc = "Field `CHR1` reader - Character Length 1"]
188pub type CHR1_R = crate::BitReader<CHR1_A>;
189#[doc = "Character Length 1\n\nValue on reset: 1"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum CHR1_A {
192    #[doc = "0: SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length"]
193    _0 = 0,
194    #[doc = "1: SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length"]
195    _1 = 1,
196}
197impl From<CHR1_A> for bool {
198    #[inline(always)]
199    fn from(variant: CHR1_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl CHR1_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> CHR1_A {
207        match self.bits {
208            false => CHR1_A::_0,
209            true => CHR1_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == CHR1_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == CHR1_A::_1
221    }
222}
223#[doc = "Field `CHR1` writer - Character Length 1"]
224pub type CHR1_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCMR_SPEC, CHR1_A, O>;
225impl<'a, const O: u8> CHR1_W<'a, O> {
226    #[doc = "SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(CHR1_A::_0)
230    }
231    #[doc = "SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length"]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(CHR1_A::_1)
235    }
236}
237#[doc = "Field `BCP2` reader - Base Clock Pulse 2"]
238pub type BCP2_R = crate::BitReader<bool>;
239#[doc = "Field `BCP2` writer - Base Clock Pulse 2"]
240pub type BCP2_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCMR_SPEC, bool, O>;
241impl R {
242    #[doc = "Bit 0 - Smart Card Interface Mode Select"]
243    #[inline(always)]
244    pub fn smif(&self) -> SMIF_R {
245        SMIF_R::new((self.bits & 1) != 0)
246    }
247    #[doc = "Bit 2 - Transmitted/Received Data Invert"]
248    #[inline(always)]
249    pub fn sinv(&self) -> SINV_R {
250        SINV_R::new(((self.bits >> 2) & 1) != 0)
251    }
252    #[doc = "Bit 3 - Transmitted/Received Data Transfer Direction"]
253    #[inline(always)]
254    pub fn sdir(&self) -> SDIR_R {
255        SDIR_R::new(((self.bits >> 3) & 1) != 0)
256    }
257    #[doc = "Bit 4 - Character Length 1"]
258    #[inline(always)]
259    pub fn chr1(&self) -> CHR1_R {
260        CHR1_R::new(((self.bits >> 4) & 1) != 0)
261    }
262    #[doc = "Bit 7 - Base Clock Pulse 2"]
263    #[inline(always)]
264    pub fn bcp2(&self) -> BCP2_R {
265        BCP2_R::new(((self.bits >> 7) & 1) != 0)
266    }
267}
268impl W {
269    #[doc = "Bit 0 - Smart Card Interface Mode Select"]
270    #[inline(always)]
271    #[must_use]
272    pub fn smif(&mut self) -> SMIF_W<0> {
273        SMIF_W::new(self)
274    }
275    #[doc = "Bit 2 - Transmitted/Received Data Invert"]
276    #[inline(always)]
277    #[must_use]
278    pub fn sinv(&mut self) -> SINV_W<2> {
279        SINV_W::new(self)
280    }
281    #[doc = "Bit 3 - Transmitted/Received Data Transfer Direction"]
282    #[inline(always)]
283    #[must_use]
284    pub fn sdir(&mut self) -> SDIR_W<3> {
285        SDIR_W::new(self)
286    }
287    #[doc = "Bit 4 - Character Length 1"]
288    #[inline(always)]
289    #[must_use]
290    pub fn chr1(&mut self) -> CHR1_W<4> {
291        CHR1_W::new(self)
292    }
293    #[doc = "Bit 7 - Base Clock Pulse 2"]
294    #[inline(always)]
295    #[must_use]
296    pub fn bcp2(&mut self) -> BCP2_W<7> {
297        BCP2_W::new(self)
298    }
299    #[doc = "Writes raw bits to the register."]
300    #[inline(always)]
301    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
302        self.0.bits(bits);
303        self
304    }
305}
306#[doc = "Smart Card Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scmr](index.html) module"]
307pub struct SCMR_SPEC;
308impl crate::RegisterSpec for SCMR_SPEC {
309    type Ux = u8;
310}
311#[doc = "`read()` method returns [scmr::R](R) reader structure"]
312impl crate::Readable for SCMR_SPEC {
313    type Reader = R;
314}
315#[doc = "`write(|w| ..)` method takes [scmr::W](W) writer structure"]
316impl crate::Writable for SCMR_SPEC {
317    type Writer = W;
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320}
321#[doc = "`reset()` method sets SCMR to value 0xf2"]
322impl crate::Resettable for SCMR_SPEC {
323    const RESET_VALUE: Self::Ux = 0xf2;
324}
ra4m2/sci0/scmr.rs

ra4m2/sci0/
scmr.rs
