r528_pac/csic/
csic_parser0.rs1#[doc = "PRS_EN_REG register accessor: an alias for `Reg<PRS_EN_REG_SPEC>`"]
2pub type PRS_EN_REG = crate::Reg<prs_en_reg::PRS_EN_REG_SPEC>;
3#[doc = "Parser Enable Register"]
4pub mod prs_en_reg;
5#[doc = "PRS_NCSIC_IF_CFG_REG register accessor: an alias for `Reg<PRS_NCSIC_IF_CFG_REG_SPEC>`"]
6pub type PRS_NCSIC_IF_CFG_REG = crate::Reg<prs_ncsic_if_cfg_reg::PRS_NCSIC_IF_CFG_REG_SPEC>;
7#[doc = "Parser NCSIC Interface Configuration Register"]
8pub mod prs_ncsic_if_cfg_reg;
9#[doc = "PRS_CAP_REG register accessor: an alias for `Reg<PRS_CAP_REG_SPEC>`"]
10pub type PRS_CAP_REG = crate::Reg<prs_cap_reg::PRS_CAP_REG_SPEC>;
11#[doc = "Parser Capture Register"]
12pub mod prs_cap_reg;
13#[doc = "CSIC_PRS_SIGNAL_STA_REG register accessor: an alias for `Reg<CSIC_PRS_SIGNAL_STA_REG_SPEC>`"]
14pub type CSIC_PRS_SIGNAL_STA_REG =
15 crate::Reg<csic_prs_signal_sta_reg::CSIC_PRS_SIGNAL_STA_REG_SPEC>;
16#[doc = "CSIC Parser Signal Status Register"]
17pub mod csic_prs_signal_sta_reg;
18#[doc = "CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG_SPEC>`"]
19pub type CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG =
20 crate::Reg<csic_prs_ncsic_bt656_head_cfg_reg::CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG_SPEC>;
21#[doc = "CSIC Parser NCSIC BT656 Header Configuration Register"]
22pub mod csic_prs_ncsic_bt656_head_cfg_reg;
23#[doc = "PRS_C0_INFMT_REG register accessor: an alias for `Reg<PRS_C0_INFMT_REG_SPEC>`"]
24pub type PRS_C0_INFMT_REG = crate::Reg<prs_c0_infmt_reg::PRS_C0_INFMT_REG_SPEC>;
25#[doc = "Parser Channel_0 Input Format Register"]
26pub mod prs_c0_infmt_reg;
27#[doc = "PRS_C0_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C0_OUTPUT_HSIZE_REG_SPEC>`"]
28pub type PRS_C0_OUTPUT_HSIZE_REG =
29 crate::Reg<prs_c0_output_hsize_reg::PRS_C0_OUTPUT_HSIZE_REG_SPEC>;
30#[doc = "Parser Channel_0 Output Horizontal Size Register"]
31pub mod prs_c0_output_hsize_reg;
32#[doc = "PRS_C0_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C0_OUTPUT_VSIZE_REG_SPEC>`"]
33pub type PRS_C0_OUTPUT_VSIZE_REG =
34 crate::Reg<prs_c0_output_vsize_reg::PRS_C0_OUTPUT_VSIZE_REG_SPEC>;
35#[doc = "Parser Channel_0 Output Vertical Size Register"]
36pub mod prs_c0_output_vsize_reg;
37#[doc = "PRS_C0_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA0_REG_SPEC>`"]
38pub type PRS_C0_INPUT_PARA0_REG = crate::Reg<prs_c0_input_para0_reg::PRS_C0_INPUT_PARA0_REG_SPEC>;
39#[doc = "Parser Channel_0 Input Parameter0 Register"]
40pub mod prs_c0_input_para0_reg;
41#[doc = "PRS_C0_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA1_REG_SPEC>`"]
42pub type PRS_C0_INPUT_PARA1_REG = crate::Reg<prs_c0_input_para1_reg::PRS_C0_INPUT_PARA1_REG_SPEC>;
43#[doc = "Parser Channel_0 Input Parameter1 Register"]
44pub mod prs_c0_input_para1_reg;
45#[doc = "PRS_C0_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA2_REG_SPEC>`"]
46pub type PRS_C0_INPUT_PARA2_REG = crate::Reg<prs_c0_input_para2_reg::PRS_C0_INPUT_PARA2_REG_SPEC>;
47#[doc = "Parser Channel_0 Input Parameter2 Register"]
48pub mod prs_c0_input_para2_reg;
49#[doc = "PRS_C0_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA3_REG_SPEC>`"]
50pub type PRS_C0_INPUT_PARA3_REG = crate::Reg<prs_c0_input_para3_reg::PRS_C0_INPUT_PARA3_REG_SPEC>;
51#[doc = "Parser Channel_0 Input Parameter3 Register"]
52pub mod prs_c0_input_para3_reg;
53#[doc = "PRS_C0_INT_EN_REG register accessor: an alias for `Reg<PRS_C0_INT_EN_REG_SPEC>`"]
54pub type PRS_C0_INT_EN_REG = crate::Reg<prs_c0_int_en_reg::PRS_C0_INT_EN_REG_SPEC>;
55#[doc = "Parser Channel_0 Interrupt Enable Register"]
56pub mod prs_c0_int_en_reg;
57#[doc = "PRS_C0_INT_STA_REG register accessor: an alias for `Reg<PRS_C0_INT_STA_REG_SPEC>`"]
58pub type PRS_C0_INT_STA_REG = crate::Reg<prs_c0_int_sta_reg::PRS_C0_INT_STA_REG_SPEC>;
59#[doc = "Parser Channel_0 Interrupt Status Register"]
60pub mod prs_c0_int_sta_reg;
61#[doc = "PRS_CH0_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH0_LINE_TIME_REG_SPEC>`"]
62pub type PRS_CH0_LINE_TIME_REG = crate::Reg<prs_ch0_line_time_reg::PRS_CH0_LINE_TIME_REG_SPEC>;
63#[doc = "Parser Channel_0 Line Time Register"]
64pub mod prs_ch0_line_time_reg;
65#[doc = "PRS_C1_INFMT_REG register accessor: an alias for `Reg<PRS_C1_INFMT_REG_SPEC>`"]
66pub type PRS_C1_INFMT_REG = crate::Reg<prs_c1_infmt_reg::PRS_C1_INFMT_REG_SPEC>;
67#[doc = "Parser Channel_1 Input Format Register"]
68pub mod prs_c1_infmt_reg;
69#[doc = "PRS_C1_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C1_OUTPUT_HSIZE_REG_SPEC>`"]
70pub type PRS_C1_OUTPUT_HSIZE_REG =
71 crate::Reg<prs_c1_output_hsize_reg::PRS_C1_OUTPUT_HSIZE_REG_SPEC>;
72#[doc = "Parser Channel_1 Output Horizontal Size"]
73pub mod prs_c1_output_hsize_reg;
74#[doc = "PRS_C1_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C1_OUTPUT_VSIZE_REG_SPEC>`"]
75pub type PRS_C1_OUTPUT_VSIZE_REG =
76 crate::Reg<prs_c1_output_vsize_reg::PRS_C1_OUTPUT_VSIZE_REG_SPEC>;
77#[doc = "Parser Channel_1 Output Vertical Size Register"]
78pub mod prs_c1_output_vsize_reg;
79#[doc = "PRS_C1_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA0_REG_SPEC>`"]
80pub type PRS_C1_INPUT_PARA0_REG = crate::Reg<prs_c1_input_para0_reg::PRS_C1_INPUT_PARA0_REG_SPEC>;
81#[doc = "Parser Channel_1 Input Parameter0 Register"]
82pub mod prs_c1_input_para0_reg;
83#[doc = "PRS_C1_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA1_REG_SPEC>`"]
84pub type PRS_C1_INPUT_PARA1_REG = crate::Reg<prs_c1_input_para1_reg::PRS_C1_INPUT_PARA1_REG_SPEC>;
85#[doc = "Parser Channel_1 Input Parameter1 Register"]
86pub mod prs_c1_input_para1_reg;
87#[doc = "PRS_C1_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA2_REG_SPEC>`"]
88pub type PRS_C1_INPUT_PARA2_REG = crate::Reg<prs_c1_input_para2_reg::PRS_C1_INPUT_PARA2_REG_SPEC>;
89#[doc = "Parser Channel_1 Input Parameter2 Register"]
90pub mod prs_c1_input_para2_reg;
91#[doc = "PRS_C1_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA3_REG_SPEC>`"]
92pub type PRS_C1_INPUT_PARA3_REG = crate::Reg<prs_c1_input_para3_reg::PRS_C1_INPUT_PARA3_REG_SPEC>;
93#[doc = "Parser Channel_1 Input Parameter3 Register"]
94pub mod prs_c1_input_para3_reg;
95#[doc = "PRS_C1_INT_EN_REG register accessor: an alias for `Reg<PRS_C1_INT_EN_REG_SPEC>`"]
96pub type PRS_C1_INT_EN_REG = crate::Reg<prs_c1_int_en_reg::PRS_C1_INT_EN_REG_SPEC>;
97#[doc = "Parser Channel_1 Interrupt Enable Register"]
98pub mod prs_c1_int_en_reg;
99#[doc = "PRS_C1_INT_STA_REG register accessor: an alias for `Reg<PRS_C1_INT_STA_REG_SPEC>`"]
100pub type PRS_C1_INT_STA_REG = crate::Reg<prs_c1_int_sta_reg::PRS_C1_INT_STA_REG_SPEC>;
101#[doc = "Parser Channel_1 Interrupt Status Register"]
102pub mod prs_c1_int_sta_reg;
103#[doc = "PRS_CH1_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH1_LINE_TIME_REG_SPEC>`"]
104pub type PRS_CH1_LINE_TIME_REG = crate::Reg<prs_ch1_line_time_reg::PRS_CH1_LINE_TIME_REG_SPEC>;
105#[doc = "Parser Channel_1 Line Time Register"]
106pub mod prs_ch1_line_time_reg;
107#[doc = "PRS_C2_INFMT_REG register accessor: an alias for `Reg<PRS_C2_INFMT_REG_SPEC>`"]
108pub type PRS_C2_INFMT_REG = crate::Reg<prs_c2_infmt_reg::PRS_C2_INFMT_REG_SPEC>;
109#[doc = "Parser Channel_2 Input Format Register"]
110pub mod prs_c2_infmt_reg;
111#[doc = "PRS_C2_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C2_OUTPUT_HSIZE_REG_SPEC>`"]
112pub type PRS_C2_OUTPUT_HSIZE_REG =
113 crate::Reg<prs_c2_output_hsize_reg::PRS_C2_OUTPUT_HSIZE_REG_SPEC>;
114#[doc = "Parser Channel_2 Output Horizontal Size Register"]
115pub mod prs_c2_output_hsize_reg;
116#[doc = "PRS_C2_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C2_OUTPUT_VSIZE_REG_SPEC>`"]
117pub type PRS_C2_OUTPUT_VSIZE_REG =
118 crate::Reg<prs_c2_output_vsize_reg::PRS_C2_OUTPUT_VSIZE_REG_SPEC>;
119#[doc = "Parser Channel_2 Output Vertical Size Register"]
120pub mod prs_c2_output_vsize_reg;
121#[doc = "PRS_C2_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA0_REG_SPEC>`"]
122pub type PRS_C2_INPUT_PARA0_REG = crate::Reg<prs_c2_input_para0_reg::PRS_C2_INPUT_PARA0_REG_SPEC>;
123#[doc = "Parser Channel_2 Input Parameter0 Register"]
124pub mod prs_c2_input_para0_reg;
125#[doc = "PRS_C2_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA1_REG_SPEC>`"]
126pub type PRS_C2_INPUT_PARA1_REG = crate::Reg<prs_c2_input_para1_reg::PRS_C2_INPUT_PARA1_REG_SPEC>;
127#[doc = "Parser Channel_2 Input Parameter1 Register"]
128pub mod prs_c2_input_para1_reg;
129#[doc = "PRS_C2_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA2_REG_SPEC>`"]
130pub type PRS_C2_INPUT_PARA2_REG = crate::Reg<prs_c2_input_para2_reg::PRS_C2_INPUT_PARA2_REG_SPEC>;
131#[doc = "Parser Channel_2 Input Parameter2 Register"]
132pub mod prs_c2_input_para2_reg;
133#[doc = "PRS_C2_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA3_REG_SPEC>`"]
134pub type PRS_C2_INPUT_PARA3_REG = crate::Reg<prs_c2_input_para3_reg::PRS_C2_INPUT_PARA3_REG_SPEC>;
135#[doc = "Parser Channel_2 Input Parameter3 Register"]
136pub mod prs_c2_input_para3_reg;
137#[doc = "PRS_C2_INT_EN_REG register accessor: an alias for `Reg<PRS_C2_INT_EN_REG_SPEC>`"]
138pub type PRS_C2_INT_EN_REG = crate::Reg<prs_c2_int_en_reg::PRS_C2_INT_EN_REG_SPEC>;
139#[doc = "Parser Channel_2 Interrupt Enable Register"]
140pub mod prs_c2_int_en_reg;
141#[doc = "PRS_C2_INT_STA_REG register accessor: an alias for `Reg<PRS_C2_INT_STA_REG_SPEC>`"]
142pub type PRS_C2_INT_STA_REG = crate::Reg<prs_c2_int_sta_reg::PRS_C2_INT_STA_REG_SPEC>;
143#[doc = "Parser Channel_2 Interrupt Status Register"]
144pub mod prs_c2_int_sta_reg;
145#[doc = "PRS_CH2_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH2_LINE_TIME_REG_SPEC>`"]
146pub type PRS_CH2_LINE_TIME_REG = crate::Reg<prs_ch2_line_time_reg::PRS_CH2_LINE_TIME_REG_SPEC>;
147#[doc = "Parser Channel_2 Line Time Register"]
148pub mod prs_ch2_line_time_reg;
149#[doc = "PRS_C3_INFMT_REG register accessor: an alias for `Reg<PRS_C3_INFMT_REG_SPEC>`"]
150pub type PRS_C3_INFMT_REG = crate::Reg<prs_c3_infmt_reg::PRS_C3_INFMT_REG_SPEC>;
151#[doc = "Parser Channel_3 Input Format Register"]
152pub mod prs_c3_infmt_reg;
153#[doc = "PRS_C3_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C3_OUTPUT_HSIZE_REG_SPEC>`"]
154pub type PRS_C3_OUTPUT_HSIZE_REG =
155 crate::Reg<prs_c3_output_hsize_reg::PRS_C3_OUTPUT_HSIZE_REG_SPEC>;
156#[doc = "Parser Channel_3 Output Horizontal Size Register"]
157pub mod prs_c3_output_hsize_reg;
158#[doc = "PRS_C3_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C3_OUTPUT_VSIZE_REG_SPEC>`"]
159pub type PRS_C3_OUTPUT_VSIZE_REG =
160 crate::Reg<prs_c3_output_vsize_reg::PRS_C3_OUTPUT_VSIZE_REG_SPEC>;
161#[doc = "Parser Channel_3 Output Vertical Size Register"]
162pub mod prs_c3_output_vsize_reg;
163#[doc = "PRS_C3_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA0_REG_SPEC>`"]
164pub type PRS_C3_INPUT_PARA0_REG = crate::Reg<prs_c3_input_para0_reg::PRS_C3_INPUT_PARA0_REG_SPEC>;
165#[doc = "Parser Channel_3 Input Parameter0 Register"]
166pub mod prs_c3_input_para0_reg;
167#[doc = "PRS_C3_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA1_REG_SPEC>`"]
168pub type PRS_C3_INPUT_PARA1_REG = crate::Reg<prs_c3_input_para1_reg::PRS_C3_INPUT_PARA1_REG_SPEC>;
169#[doc = "Parser Channel_3 Input Parameter1 Register"]
170pub mod prs_c3_input_para1_reg;
171#[doc = "PRS_C3_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA2_REG_SPEC>`"]
172pub type PRS_C3_INPUT_PARA2_REG = crate::Reg<prs_c3_input_para2_reg::PRS_C3_INPUT_PARA2_REG_SPEC>;
173#[doc = "Parser Channel_3 Input Parameter2 Register"]
174pub mod prs_c3_input_para2_reg;
175#[doc = "PRS_C3_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA3_REG_SPEC>`"]
176pub type PRS_C3_INPUT_PARA3_REG = crate::Reg<prs_c3_input_para3_reg::PRS_C3_INPUT_PARA3_REG_SPEC>;
177#[doc = "Parser Channel_3 Input Parameter3 Register"]
178pub mod prs_c3_input_para3_reg;
179#[doc = "PRS_C3_INT_EN_REG register accessor: an alias for `Reg<PRS_C3_INT_EN_REG_SPEC>`"]
180pub type PRS_C3_INT_EN_REG = crate::Reg<prs_c3_int_en_reg::PRS_C3_INT_EN_REG_SPEC>;
181#[doc = "Parser Channel_3 Interrupt Enable Register"]
182pub mod prs_c3_int_en_reg;
183#[doc = "PRS_C3_INT_STA_REG register accessor: an alias for `Reg<PRS_C3_INT_STA_REG_SPEC>`"]
184pub type PRS_C3_INT_STA_REG = crate::Reg<prs_c3_int_sta_reg::PRS_C3_INT_STA_REG_SPEC>;
185#[doc = "Parser Channel_3 Interrupt Status Register"]
186pub mod prs_c3_int_sta_reg;
187#[doc = "PRS_CH3_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH3_LINE_TIME_REG_SPEC>`"]
188pub type PRS_CH3_LINE_TIME_REG = crate::Reg<prs_ch3_line_time_reg::PRS_CH3_LINE_TIME_REG_SPEC>;
189#[doc = "Parser Channel_3 Line Time Register"]
190pub mod prs_ch3_line_time_reg;
191#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_SPEC>`"]
192pub type CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG =
193 crate::Reg<csic_prs_ncsic_rx_signal0_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_SPEC>;
194#[doc = "CSIC Parser NCSIC RX Signal0 Delay Adjust Register"]
195pub mod csic_prs_ncsic_rx_signal0_dly_adj_reg;
196#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG_SPEC>`"]
197pub type CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG =
198 crate::Reg<csic_prs_ncsic_rx_signal5_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG_SPEC>;
199#[doc = "CSIC Parser NCSIC RX Signal5 Delay Adjust Register"]
200pub mod csic_prs_ncsic_rx_signal5_dly_adj_reg;
201#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG_SPEC>`"]
202pub type CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG =
203 crate::Reg<csic_prs_ncsic_rx_signal6_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG_SPEC>;
204#[doc = "CSIC Parser NCSIC RX Signal6 Delay Adjust Register"]
205pub mod csic_prs_ncsic_rx_signal6_dly_adj_reg;