Struct qn908x_rs::ctimer0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ir: IR,
    pub tcr: TCR,
    pub tc: TC,
    pub pr: PR,
    pub pc: PC,
    pub mcr: MCR,
    pub ccr: CCR,
    pub emr: EMR,
    pub ctcr: CTCR,
    pub pwmc: PWMC,
    // some fields omitted
}

Register block

Fields

ir: IR

0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

tcr: TCR

0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

tc: TC

0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.

pr: PR

0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.

pc: PC

0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

mcr: MCR

0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

ccr: CCR

0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

emr: EMR

0x3c - External Match Register. The EMR controls the match function and the external match pins.

ctcr: CTCR

0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

pwmc: PWMC

0x74 - PWM Control Register. The PWMCON enables PWM mode for the external match pins.

Trait Implementations