[−][src]Trait probe_rs::CoreInterface
Required methods
fn wait_for_core_halted(&self) -> Result<(), Error>
Wait until the core is halted. If the core does not halt on its own,
a DebugProbeError::Timeout
error will be returned.
fn core_halted(&self) -> Result<bool, Error>
Check if the core is halted. If the core does not halt on its own,
a CoreError::Timeout
error will be returned.
fn halt(&self) -> Result<CoreInformation, Error>
Try to halt the core. This function ensures the core is actually halted, and
returns a CoreError::Timeout
otherwise.
fn run(&self) -> Result<(), Error>
fn reset(&self) -> Result<(), Error>
Reset the core, and then continue to execute instructions. If the core
should be halted after reset, use the reset_and_halt
function.
fn reset_and_halt(&self) -> Result<CoreInformation, Error>
Reset the core, and then immediately halt. To continue execution after
reset, use the reset
function.
fn step(&self) -> Result<CoreInformation, Error>
Steps one instruction and then enters halted state again.
fn read_core_reg(&self, address: CoreRegisterAddress) -> Result<u32, Error>
fn write_core_reg(
&self,
address: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
&self,
address: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
fn get_available_breakpoint_units(&self) -> Result<u32, Error>
fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
fn set_breakpoint(&self, bp_unit_index: usize, addr: u32) -> Result<(), Error>
fn clear_breakpoint(&self, unit_index: usize) -> Result<(), Error>
fn registers(&self) -> &'static RegisterFile
fn memory(&self) -> Memory
fn hw_breakpoints_enabled(&self) -> bool
fn architecture(&self) -> Architecture
Implementors
impl CoreInterface for M0
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fn wait_for_core_halted(&self) -> Result<(), Error>
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fn core_halted(&self) -> Result<bool, Error>
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fn read_core_reg(&self, addr: CoreRegisterAddress) -> Result<u32, Error>
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fn write_core_reg(
&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
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&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
fn halt(&self) -> Result<CoreInformation, Error>
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fn run(&self) -> Result<(), Error>
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fn step(&self) -> Result<CoreInformation, Error>
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fn reset(&self) -> Result<(), Error>
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fn reset_and_halt(&self) -> Result<CoreInformation, Error>
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fn get_available_breakpoint_units(&self) -> Result<u32, Error>
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fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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fn set_breakpoint(
&self,
bp_register_index: usize,
addr: u32
) -> Result<(), Error>
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&self,
bp_register_index: usize,
addr: u32
) -> Result<(), Error>
fn registers(&self) -> &'static RegisterFile
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fn clear_breakpoint(&self, bp_unit_index: usize) -> Result<(), Error>
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fn memory(&self) -> Memory
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fn hw_breakpoints_enabled(&self) -> bool
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fn architecture(&self) -> Architecture
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impl CoreInterface for M33
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fn wait_for_core_halted(&self) -> Result<(), Error>
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fn core_halted(&self) -> Result<bool, Error>
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fn halt(&self) -> Result<CoreInformation, Error>
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fn run(&self) -> Result<(), Error>
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fn reset(&self) -> Result<(), Error>
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fn reset_and_halt(&self) -> Result<CoreInformation, Error>
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fn step(&self) -> Result<CoreInformation, Error>
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fn read_core_reg(&self, addr: CoreRegisterAddress) -> Result<u32, Error>
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fn write_core_reg(
&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
[src]
&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
fn get_available_breakpoint_units(&self) -> Result<u32, Error>
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fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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fn set_breakpoint(&self, bp_unit_index: usize, addr: u32) -> Result<(), Error>
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fn registers(&self) -> &'static RegisterFile
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fn clear_breakpoint(&self, bp_unit_index: usize) -> Result<(), Error>
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fn memory(&self) -> Memory
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fn hw_breakpoints_enabled(&self) -> bool
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fn architecture(&self) -> Architecture
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impl CoreInterface for M4
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fn wait_for_core_halted(&self) -> Result<(), Error>
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fn core_halted(&self) -> Result<bool, Error>
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fn read_core_reg(&self, addr: CoreRegisterAddress) -> Result<u32, Error>
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fn write_core_reg(
&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
[src]
&self,
addr: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
fn halt(&self) -> Result<CoreInformation, Error>
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fn run(&self) -> Result<(), Error>
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fn step(&self) -> Result<CoreInformation, Error>
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fn reset(&self) -> Result<(), Error>
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fn reset_and_halt(&self) -> Result<CoreInformation, Error>
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fn get_available_breakpoint_units(&self) -> Result<u32, Error>
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fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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fn set_breakpoint(&self, bp_unit_index: usize, addr: u32) -> Result<(), Error>
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fn registers(&self) -> &'static RegisterFile
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fn clear_breakpoint(&self, bp_unit_index: usize) -> Result<(), Error>
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fn memory(&self) -> Memory
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fn hw_breakpoints_enabled(&self) -> bool
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fn architecture(&self) -> Architecture
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impl CoreInterface for Riscv32
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fn wait_for_core_halted(&self) -> Result<(), Error>
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fn core_halted(&self) -> Result<bool, Error>
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fn halt(&self) -> Result<CoreInformation, Error>
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fn run(&self) -> Result<(), Error>
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fn reset(&self) -> Result<(), Error>
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fn reset_and_halt(&self) -> Result<CoreInformation, Error>
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fn step(&self) -> Result<CoreInformation, Error>
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fn read_core_reg(&self, address: CoreRegisterAddress) -> Result<u32, Error>
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fn write_core_reg(
&self,
address: CoreRegisterAddress,
value: u32
) -> Result<(), Error>
[src]
&self,
address: CoreRegisterAddress,
value: u32
) -> Result<(), Error>