[−][src]Trait probe_rs::target::Core

pub trait Core: Debug + DynClone + Sync + Send {
    fn wait_for_core_halted(
        &self, 
        mi: &mut MasterProbe
    ) -> Result<(), DebugProbeError>;

    fn core_halted(&self, mi: &mut MasterProbe) -> Result<bool, DebugProbeError>;

    fn halt(
        &self, 
        mi: &mut MasterProbe
    ) -> Result<CoreInformation, DebugProbeError>;

    fn run(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError>;

    fn reset(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError>;

    fn reset_and_halt(
        &self, 
        mi: &mut MasterProbe
    ) -> Result<CoreInformation, DebugProbeError>;

    fn step(
        &self, 
        mi: &mut MasterProbe
    ) -> Result<CoreInformation, DebugProbeError>;

    fn read_core_reg(
        &self, 
        mi: &mut MasterProbe, 
        addr: CoreRegisterAddress
    ) -> Result<u32, DebugProbeError>;

    fn write_core_reg(
        &self, 
        mi: &mut MasterProbe, 
        addr: CoreRegisterAddress, 
        value: u32
    ) -> Result<(), DebugProbeError>;

    fn get_available_breakpoint_units(
        &self, 
        mi: &mut MasterProbe
    ) -> Result<u32, DebugProbeError>;

    fn enable_breakpoints(
        &self, 
        mi: &mut MasterProbe, 
        state: bool
    ) -> Result<(), DebugProbeError>;

    fn set_breakpoint(
        &self, 
        mi: &mut MasterProbe, 
        bp_unit_index: usize, 
        addr: u32
    ) -> Result<(), DebugProbeError>;

    fn clear_breakpoint(
        &self, 
        mi: &mut MasterProbe, 
        bp_unit_index: usize
    ) -> Result<(), DebugProbeError>;

    fn read_block8(
        &self, 
        mi: &mut MasterProbe, 
        address: u32, 
        data: &mut [u8]
    ) -> Result<(), DebugProbeError>;

    fn registers<'a>(&self) -> &'a BasicRegisterAddresses;
}

Required methods

fn wait_for_core_halted(
    &self,
    mi: &mut MasterProbe
) -> Result<(), DebugProbeError>

Wait until the core is halted. If the core does not halt on its own, a DebugProbeError::Timeout error will be returned.

fn core_halted(&self, mi: &mut MasterProbe) -> Result<bool, DebugProbeError>

Check if the core is halted. If the core does not halt on its own, a DebugProbeError::Timeout error will be returned.

fn halt(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError>

Try to halt the core. This function ensures the core is actually halted, and returns a DebugProbeError::Timeout otherwise.

fn run(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError>

fn reset(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError>

Reset the core, and then continue to execute instructions. If the core should be halted after reset, use the reset_and_halt function.

fn reset_and_halt(
    &self,
    mi: &mut MasterProbe
) -> Result<CoreInformation, DebugProbeError>

Reset the core, and then immediately halt. To continue execution after reset, use the reset function.

fn step(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError>

Steps one instruction and then enters halted state again.

fn read_core_reg(
    &self,
    mi: &mut MasterProbe,
    addr: CoreRegisterAddress
) -> Result<u32, DebugProbeError>

fn write_core_reg(
    &self,
    mi: &mut MasterProbe,
    addr: CoreRegisterAddress,
    value: u32
) -> Result<(), DebugProbeError>

fn get_available_breakpoint_units(
    &self,
    mi: &mut MasterProbe
) -> Result<u32, DebugProbeError>

fn enable_breakpoints(
    &self,
    mi: &mut MasterProbe,
    state: bool
) -> Result<(), DebugProbeError>

fn set_breakpoint(
    &self,
    mi: &mut MasterProbe,
    bp_unit_index: usize,
    addr: u32
) -> Result<(), DebugProbeError>

fn clear_breakpoint(
    &self,
    mi: &mut MasterProbe,
    bp_unit_index: usize
) -> Result<(), DebugProbeError>

fn read_block8(
    &self,
    mi: &mut MasterProbe,
    address: u32,
    data: &mut [u8]
) -> Result<(), DebugProbeError>

fn registers<'a>(&self) -> &'a BasicRegisterAddresses

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Implementors

impl Core for FakeM0[src]

fn step(
    &self,
    _mi: &mut MasterProbe
) -> Result<CoreInformation, DebugProbeError>[src]

Steps one instruction and then enters halted state again.

impl Core for M0[src]

impl Core for M33[src]

impl Core for M4[src]

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