Expand description
Debugging toolset for embedded devices
Prerequisites
- Udev rules
- libusb
Examples
Halting the attached chip
use probe_rs::{Probe, Permissions};
// Get a list of all available debug probes.
let probes = Probe::list_all();
// Use the first probe found.
let mut probe = probes[0].open()?;
// Attach to a chip.
let mut session = probe.attach("nrf52", Permissions::default())?;
// Select a core.
let mut core = session.core(0)?;
// Halt the attached core.
core.halt(std::time::Duration::from_millis(10))?;Reading from RAM
use probe_rs::{Session, Permissions};
use probe_rs::MemoryInterface;
let mut session = Session::auto_attach("nrf52", Permissions::default())?;
let mut core = session.core(0)?;
// Read a block of 50 32 bit words.
let mut buff = [0u32;50];
core.read_32(0x2000_0000, &mut buff)?;
// Read a single 32 bit word.
let word = core.read_word_32(0x2000_0000)?;
// Writing is just as simple.
let buff = [0u32;50];
core.write_32(0x2000_0000, &buff)?;
// of course we can also write 8bit words.
let buff = [0u8;50];
core.write_8(0x2000_0000, &buff)?;
probe-rs is built around 5 main interfaces: the Probe, Target, Session, Memory and Core strucs.
Modules
All the interface bits for the different architectures.
Target specific configuration
Debugging support for probe-rs
Flash programming operations.
Macros
Defines a new typed access port.
Defines a new typed access port register for a specific access port. Takes
Defines a new debug port register for typed access.
Structs
The id of a breakpoint.
Generic core handle representing a physical core on an MCU.
An struct for storing the current state of a core.
A generic core state which caches the generic parts of the core state.
Gathers some information about a debug probe which was found during a scan.
A struct to describe the way a probe should be selected.
This is a mock probe which can be used for mocking things in tests or for dry runs.
A struct to allow memory access via an ARM probe.
The Permissions struct represents what a Session is allowed to do with a target.
Some operations can be irreversable, so need to be explicitly allowed by the user.
The Probe struct is a generic wrapper over the different probes supported.
Describes a register with its properties.
Register description for a core.
The location of a CPU \register. This is not an actual memory address, but a core specific location that represents a specific core register.
The Session struct represents an active debug session.
This describes a complete target with a fixed chip model and variant.
Enums
The architecture family of a specific CoreType.
The method that should be used for attaching.
The status of the core.
Type of a supported core.
This error occurs whenever the debug probe logic encounters an error while operating the relevant debug probe.
Denotes the type of a given DebugProbe.
The overarching error type which contains all possible errors as variants.
The reason why a core was halted.
Instruction set used by a core
An error during probe creation accured. This is almost always a sign of a bad USB setup. Check UDEV rules if you are on Linux and try installing Zadig (This will disable vendor specific drivers for your probe!) if you are on Windows.
A value of a core register
The architecture specific core state.
The protocol that is to be used by the probe when communicating with the target.
Traits
A helper trait to get more specific interfaces.
A generic interface to control a MCU core.
An abstraction over general debug probe functionality.
An interface to be implemented for drivers that allow target memory access.
A memory mapped register, for instance ARM debug registers (DHCSR, etc).