Struct pci_types::EndpointHeader

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pub struct EndpointHeader(/* private fields */);

Expand description

Endpoints have a Type-0 header, so the remainder of the header is of the form:

    32                           16                              0
    +-----------------------------------------------------------+ 0x00
    |                                                           |
    |                Predefined region of header                |
    |                                                           |
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 0                  | 0x10
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 1                  | 0x14
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 2                  | 0x18
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 3                  | 0x1c
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 4                  | 0x20
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 5                  | 0x24
    |                                                           |
    +-----------------------------------------------------------+
    |                  CardBus CIS Pointer                      | 0x28
    |                                                           |
    +----------------------------+------------------------------+
    |       Subsystem ID         |    Subsystem vendor ID       | 0x2c
    |                            |                              |
    +----------------------------+------------------------------+
    |               Expansion ROM Base Address                  | 0x30
    |                                                           |
    +--------------------------------------------+--------------+
    |                 Reserved                   | Capabilities | 0x34
    |                                            |   Pointer    |
    +--------------------------------------------+--------------+
    |                         Reserved                          | 0x38
    |                                                           |
    +--------------+--------------+--------------+--------------+
    |   Max_Lat    |   Min_Gnt    |  Interrupt   |  Interrupt   | 0x3c
    |              |              |   pin        |   line       |
    +--------------+--------------+--------------+--------------+

Implementations§

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impl EndpointHeader

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pub fn from_header( header: PciHeader, access: &impl ConfigRegionAccess ) -> Option<EndpointHeader>

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pub fn status(&self, access: &impl ConfigRegionAccess) -> StatusRegister

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pub fn command(&self, access: &impl ConfigRegionAccess) -> CommandRegister

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pub fn update_command<F>(&self, access: &impl ConfigRegionAccess, f: F)
where F: Fn(CommandRegister) -> CommandRegister,

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pub fn capability_pointer(&self, access: &impl ConfigRegionAccess) -> u16

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pub fn capabilities<'a, T: ConfigRegionAccess>( &self, access: &'a T ) -> CapabilityIterator<'a, T> ⓘ

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pub fn subsystem( &self, access: &impl ConfigRegionAccess ) -> (SubsystemId, SubsystemVendorId)

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pub fn bar(&self, slot: u8, access: &impl ConfigRegionAccess) -> Option<Bar>

Get the contents of a BAR in a given slot. Empty bars will return None.

§Note

64-bit memory BARs use two slots, so if one is decoded in e.g. slot #0, this method should not be called for slot #1

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pub unsafe fn write_bar( &mut self, slot: u8, access: &impl ConfigRegionAccess, value: usize ) -> Result<(), BarWriteError>

Write to a BAR, setting the address for a device to use. The supplied value must be a valid BAR value (refer to the PCIe specification for requirements) and must be of the correct size (i.e. no larger than u32::MAX for 32-bit BARs). In the case of a 64-bit BAR, the supplied slot should be the first slot of the pair.

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