[−]Struct nucleo_f401re::pac::rcc::RegisterBlock
Register block
Fields
cr: Reg<u32, _CR>
0x00 - clock control register
pllcfgr: Reg<u32, _PLLCFGR>
0x04 - PLL configuration register
cfgr: Reg<u32, _CFGR>
0x08 - clock configuration register
cir: Reg<u32, _CIR>
0x0c - clock interrupt register
ahb1rstr: Reg<u32, _AHB1RSTR>
0x10 - AHB1 peripheral reset register
ahb2rstr: Reg<u32, _AHB2RSTR>
0x14 - AHB2 peripheral reset register
apb1rstr: Reg<u32, _APB1RSTR>
0x20 - APB1 peripheral reset register
apb2rstr: Reg<u32, _APB2RSTR>
0x24 - APB2 peripheral reset register
ahb1enr: Reg<u32, _AHB1ENR>
0x30 - AHB1 peripheral clock register
ahb2enr: Reg<u32, _AHB2ENR>
0x34 - AHB2 peripheral clock enable register
apb1enr: Reg<u32, _APB1ENR>
0x40 - APB1 peripheral clock enable register
apb2enr: Reg<u32, _APB2ENR>
0x44 - APB2 peripheral clock enable register
ahb1lpenr: Reg<u32, _AHB1LPENR>
0x50 - AHB1 peripheral clock enable in low power mode register
ahb2lpenr: Reg<u32, _AHB2LPENR>
0x54 - AHB2 peripheral clock enable in low power mode register
apb1lpenr: Reg<u32, _APB1LPENR>
0x60 - APB1 peripheral clock enable in low power mode register
apb2lpenr: Reg<u32, _APB2LPENR>
0x64 - APB2 peripheral clock enabled in low power mode register
bdcr: Reg<u32, _BDCR>
0x70 - Backup domain control register
csr: Reg<u32, _CSR>
0x74 - clock control & status register
sscgr: Reg<u32, _SSCGR>
0x80 - spread spectrum clock generation register
plli2scfgr: Reg<u32, _PLLI2SCFGR>
0x84 - PLLI2S configuration register
dckcfgr: Reg<u32, _DCKCFGR>
0x8c - RCC Dedicated Clock Configuration Register
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