Type Definition nuc1xx::gcr::rstsrc::W

type W = W<u32, RSTSRC>;

Writer for register RSTSRC

Methods

impl W

pub fn rsts_por(&mut self) -> RSTS_POR_W

Bit 0 - The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source 1= The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system. 0= No reset from POR or CHIP_RS Software can write 1 to clear this bit to zero.

pub fn rsts_reset(&mut self) -> RSTS_RESET_W

Bit 1 - The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. 1 = The Pin /RESET had issued the reset signal to reset the system. 0 = No reset from /RESET pin Software can write 1 to clear this bit to zero.

pub fn rsts_wdt(&mut self) -> RSTS_WDT_W

Bit 2 - The The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source. 1 = The watchdog timer had issued the reset signal to reset the system. 0 = No reset from watchdog timer Software can write 1 to clear this bit to zero.

pub fn rsts_lvr(&mut self) -> RSTS_LVR_W

Bit 3 - The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source. 1 = The LVR controller had issued the reset signal to reset the system. 0 = No reset from LVR Software can write 1 to clear this bit to zero.

pub fn rsts_bod(&mut self) -> RSTS_BOD_W

Bit 4 - The RSTS_BOD flag is set by the "reset signal" from the Brown-Out-Detector controller to indicate the previous reset source. 1 = The BOD had issued the reset signal to reset the system. 0 = No reset from BOD Software can write 1 to clear this bit to zero.

pub fn rsts_sys(&mut self) -> RSTS_SYS_W

Bit 5 - The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source. 1 = The Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel. 0 = No reset from Cortex_M0 Software can write 1 to clear this bit to zero.

pub fn rsts_cpu(&mut self) -> RSTS_CPU_W

Bit 7 - The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). 1 = The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 0 = No reset from CPU Software can write 1 to clear this bit to zero.