Crate nrf5340_app_pac
source · [−]Expand description
Peripheral access API for NRF5340_APPLICATION microcontrollers (generated using svd2rust v0.25.1 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use dcnf_ns as dcnf_s;pub use fpu_ns as fpu_s;pub use oscillators_ns as oscillators_s;pub use regulators_ns as regulators_s;pub use clock_ns as clock_s;pub use power_ns as power_s;pub use reset_ns as reset_s;pub use ctrlap_ns as ctrlap_s;pub use spim0_ns as spim0_s;pub use spis0_ns as spis0_s;pub use twim0_ns as twim0_s;pub use twis0_ns as twis0_s;pub use uarte0_ns as uarte0_s;pub use spim0_ns as spim1_ns;pub use spis0_ns as spis1_ns;pub use twim0_ns as twim1_ns;pub use twis0_ns as twis1_ns;pub use uarte0_ns as uarte1_ns;pub use spim0_ns as spim1_s;pub use spis0_ns as spis1_s;pub use twim0_ns as twim1_s;pub use twis0_ns as twis1_s;pub use uarte0_ns as uarte1_s;pub use spim0_ns as spim4_ns;pub use spim0_ns as spim4_s;pub use spim0_ns as spim2_ns;pub use spis0_ns as spis2_ns;pub use twim0_ns as twim2_ns;pub use twis0_ns as twis2_ns;pub use uarte0_ns as uarte2_ns;pub use spim0_ns as spim2_s;pub use spis0_ns as spis2_s;pub use twim0_ns as twim2_s;pub use twis0_ns as twis2_s;pub use uarte0_ns as uarte2_s;pub use spim0_ns as spim3_ns;pub use spis0_ns as spis3_ns;pub use twim0_ns as twim3_ns;pub use twis0_ns as twis3_ns;pub use uarte0_ns as uarte3_ns;pub use spim0_ns as spim3_s;pub use spis0_ns as spis3_s;pub use twim0_ns as twim3_s;pub use twis0_ns as twis3_s;pub use uarte0_ns as uarte3_s;pub use saadc_ns as saadc_s;pub use timer0_ns as timer0_s;pub use timer0_ns as timer1_ns;pub use timer0_ns as timer1_s;pub use timer0_ns as timer2_ns;pub use timer0_ns as timer2_s;pub use rtc0_ns as rtc0_s;pub use rtc0_ns as rtc1_ns;pub use rtc0_ns as rtc1_s;pub use dppic_ns as dppic_s;pub use wdt0_ns as wdt0_s;pub use wdt0_ns as wdt1_ns;pub use wdt0_ns as wdt1_s;pub use comp_ns as comp_s;pub use lpcomp_ns as lpcomp_s;pub use egu0_ns as egu0_s;pub use egu0_ns as egu1_ns;pub use egu0_ns as egu1_s;pub use egu0_ns as egu2_ns;pub use egu0_ns as egu2_s;pub use egu0_ns as egu3_ns;pub use egu0_ns as egu3_s;pub use egu0_ns as egu4_ns;pub use egu0_ns as egu4_s;pub use egu0_ns as egu5_ns;pub use egu0_ns as egu5_s;pub use pwm0_ns as pwm0_s;pub use pwm0_ns as pwm1_ns;pub use pwm0_ns as pwm1_s;pub use pwm0_ns as pwm2_ns;pub use pwm0_ns as pwm2_s;pub use pwm0_ns as pwm3_ns;pub use pwm0_ns as pwm3_s;pub use pdm0_ns as pdm0_s;pub use i2s0_ns as i2s0_s;pub use ipc_ns as ipc_s;pub use qspi_ns as qspi_s;pub use nfct_ns as nfct_s;pub use gpiote0_s as gpiote1_ns;pub use mutex_ns as mutex_s;pub use qdec0_ns as qdec0_s;pub use qdec0_ns as qdec1_ns;pub use qdec0_ns as qdec1_s;pub use usbd_ns as usbd_s;pub use usbregulator_ns as usbregulator_s;pub use kmu_ns as kmu_s;pub use nvmc_ns as nvmc_s;pub use p0_ns as p1_ns;pub use p0_ns as p0_s;pub use p0_ns as p1_s;pub use vmc_ns as vmc_s;Modules
Cache
CACHEDATA
CACHEINFO
Clock management 0
Comparator 0
ARM TrustZone CryptoCell register interface
Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality.
Control access port 0
Domain configuration management 0
Distributed programmable peripheral interconnect controller 0
Event generator unit 0
Factory Information Configuration Registers
FPU control peripheral 0
Common register and bit access and modify traits
GPIO Tasks and Events 0
Inter-IC Sound 0
Interprocessor communication 0
Key management unit 0
Low-power comparator 0
MUTEX 0
NFC-A compatible radio 0
Non-volatile memory controller 0
Oscillator control 0
GPIO Port 0
Pulse Density Modulation (Digital Microphone) Interface 0
Power control 0
Pulse width modulation unit 0
Quadrature Decoder 0
External flash interface 0
Voltage regulators 0
Reset control 0
Real-time counter 0
Analog to Digital Converter 0
Serial Peripheral Interface Master with EasyDMA 0
SPI Slave 0
System protection unit
Trace and debug control
Timer/Counter 0
I2C compatible Two-Wire Master Interface with EasyDMA 0
I2C compatible Two-Wire Slave Interface with EasyDMA 0
UART with EasyDMA 0
User Information Configuration Registers User information configuration registers
Universal serial bus device 0
USB Regulator 0
Volatile Memory controller 0
Watchdog Timer 0
Structs
CACHEDATA
CACHEINFO
Cache
Cache and branch predictor maintenance operations
Clock management 0
Clock management 1
Comparator 0
Comparator 1
CPUID
ARM TrustZone CryptoCell register interface
Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality.
Control access port 0
Control access port 1
Core peripherals
Debug Control Block
Domain configuration management 0
Domain configuration management 1
Distributed programmable peripheral interconnect controller 0
Distributed programmable peripheral interconnect controller 1
Data Watchpoint and Trace unit
Event generator unit 0
Event generator unit 1
Event generator unit 2
Event generator unit 3
Event generator unit 4
Event generator unit 5
Event generator unit 6
Event generator unit 7
Event generator unit 8
Event generator unit 9
Event generator unit 10
Event generator unit 11
Factory Information Configuration Registers
Flash Patch and Breakpoint unit
Floating Point Unit
FPU control peripheral 0
FPU control peripheral 1
GPIO Tasks and Events 0
GPIO Tasks and Events 1
Inter-IC Sound 0
Inter-IC Sound 1
Interprocessor communication 0
Interprocessor communication 1
Instrumentation Trace Macrocell
Key management unit 0
Key management unit 1
Low-power comparator 0
Low-power comparator 1
Memory Protection Unit
MUTEX 0
MUTEX 1
NFC-A compatible radio 0
NFC-A compatible radio 1
Nested Vector Interrupt Controller
Non-volatile memory controller 0
Non-volatile memory controller 1
Oscillator control 0
Oscillator control 1
GPIO Port 0
GPIO Port 2
GPIO Port 1
GPIO Port 3
Pulse Density Modulation (Digital Microphone) Interface 0
Pulse Density Modulation (Digital Microphone) Interface 1
Power control 0
Power control 1
Pulse width modulation unit 0
Pulse width modulation unit 1
Pulse width modulation unit 2
Pulse width modulation unit 3
Pulse width modulation unit 4
Pulse width modulation unit 5
Pulse width modulation unit 6
Pulse width modulation unit 7
All the peripherals
Quadrature Decoder 0
Quadrature Decoder 1
Quadrature Decoder 2
Quadrature Decoder 3
External flash interface 0
External flash interface 1
Voltage regulators 0
Voltage regulators 1
Reset control 0
Reset control 1
Real-time counter 0
Real-time counter 1
Real-time counter 2
Real-time counter 3
Analog to Digital Converter 0
Analog to Digital Converter 1
System Control Block
Serial Peripheral Interface Master with EasyDMA 0
Serial Peripheral Interface Master with EasyDMA 1
Serial Peripheral Interface Master with EasyDMA 2
Serial Peripheral Interface Master with EasyDMA 3
Serial Peripheral Interface Master with EasyDMA 6
Serial Peripheral Interface Master with EasyDMA 7
Serial Peripheral Interface Master with EasyDMA 8
Serial Peripheral Interface Master with EasyDMA 9
Serial Peripheral Interface Master with EasyDMA 4
Serial Peripheral Interface Master with EasyDMA 5
SPI Slave 0
SPI Slave 1
SPI Slave 2
SPI Slave 3
SPI Slave 4
SPI Slave 5
SPI Slave 6
SPI Slave 7
System protection unit
SysTick: System Timer
Trace and debug control
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
Timer/Counter 4
Timer/Counter 5
Trace Port Interface Unit
I2C compatible Two-Wire Master Interface with EasyDMA 0
I2C compatible Two-Wire Master Interface with EasyDMA 1
I2C compatible Two-Wire Master Interface with EasyDMA 2
I2C compatible Two-Wire Master Interface with EasyDMA 3
I2C compatible Two-Wire Master Interface with EasyDMA 4
I2C compatible Two-Wire Master Interface with EasyDMA 5
I2C compatible Two-Wire Master Interface with EasyDMA 6
I2C compatible Two-Wire Master Interface with EasyDMA 7
I2C compatible Two-Wire Slave Interface with EasyDMA 0
I2C compatible Two-Wire Slave Interface with EasyDMA 1
I2C compatible Two-Wire Slave Interface with EasyDMA 2
I2C compatible Two-Wire Slave Interface with EasyDMA 3
I2C compatible Two-Wire Slave Interface with EasyDMA 4
I2C compatible Two-Wire Slave Interface with EasyDMA 5
I2C compatible Two-Wire Slave Interface with EasyDMA 6
I2C compatible Two-Wire Slave Interface with EasyDMA 7
UART with EasyDMA 0
UART with EasyDMA 1
UART with EasyDMA 2
UART with EasyDMA 3
UART with EasyDMA 4
UART with EasyDMA 5
UART with EasyDMA 6
UART with EasyDMA 7
User Information Configuration Registers User information configuration registers
Universal serial bus device 0
Universal serial bus device 1
USB Regulator 0
USB Regulator 1
Volatile Memory controller 0
Volatile Memory controller 1
Watchdog Timer 0
Watchdog Timer 1
Watchdog Timer 2
Watchdog Timer 3
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority