Expand description

Configure bits to lock down CPU features at runtime

Structs

Configure bits to lock down CPU features at runtime
Register CPULOCK reader
Register CPULOCK writer

Enums

Write ‘1’ to prevent updating the Non-secure MPU regions until the next reset
Write ‘1’ to prevent updating the non-secure vector table base address until the next reset
Write ‘1’ to prevent updating the secure SAU regions until the next reset
Write ‘1’ to prevent updating the secure MPU regions until the next reset
Write ‘1’ to prevent updating the secure interrupt configuration until the next reset

Type Definitions

Field LOCKNSMPU reader - Write ‘1’ to prevent updating the Non-secure MPU regions until the next reset
Field LOCKNSMPU writer - Write ‘1’ to prevent updating the Non-secure MPU regions until the next reset
Field LOCKNSVTOR reader - Write ‘1’ to prevent updating the non-secure vector table base address until the next reset
Field LOCKNSVTOR writer - Write ‘1’ to prevent updating the non-secure vector table base address until the next reset
Field LOCKSAU reader - Write ‘1’ to prevent updating the secure SAU regions until the next reset
Field LOCKSAU writer - Write ‘1’ to prevent updating the secure SAU regions until the next reset
Field LOCKSMPU reader - Write ‘1’ to prevent updating the secure MPU regions until the next reset
Field LOCKSMPU writer - Write ‘1’ to prevent updating the secure MPU regions until the next reset
Field LOCKSVTAIRCR reader - Write ‘1’ to prevent updating the secure interrupt configuration until the next reset
Field LOCKSVTAIRCR writer - Write ‘1’ to prevent updating the secure interrupt configuration until the next reset