[−][src]Struct nrf52840_hal::target::radio::intenclr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R[src]

pub fn bits(&self) -> u32[src]

Value of the register as raw bits

pub fn ready(&self) -> READYR[src]

Bit 0 - Write '1' to disable interrupt for READY event

pub fn address(&self) -> ADDRESSR[src]

Bit 1 - Write '1' to disable interrupt for ADDRESS event

pub fn payload(&self) -> PAYLOADR[src]

Bit 2 - Write '1' to disable interrupt for PAYLOAD event

pub fn end(&self) -> ENDR[src]

Bit 3 - Write '1' to disable interrupt for END event

pub fn disabled(&self) -> DISABLEDR[src]

Bit 4 - Write '1' to disable interrupt for DISABLED event

pub fn devmatch(&self) -> DEVMATCHR[src]

Bit 5 - Write '1' to disable interrupt for DEVMATCH event

pub fn devmiss(&self) -> DEVMISSR[src]

Bit 6 - Write '1' to disable interrupt for DEVMISS event

pub fn rssiend(&self) -> RSSIENDR[src]

Bit 7 - Write '1' to disable interrupt for RSSIEND event

pub fn bcmatch(&self) -> BCMATCHR[src]

Bit 10 - Write '1' to disable interrupt for BCMATCH event

pub fn crcok(&self) -> CRCOKR[src]

Bit 12 - Write '1' to disable interrupt for CRCOK event

pub fn crcerror(&self) -> CRCERRORR[src]

Bit 13 - Write '1' to disable interrupt for CRCERROR event

pub fn framestart(&self) -> FRAMESTARTR[src]

Bit 14 - Write '1' to disable interrupt for FRAMESTART event

pub fn edend(&self) -> EDENDR[src]

Bit 15 - Write '1' to disable interrupt for EDEND event

pub fn edstopped(&self) -> EDSTOPPEDR[src]

Bit 16 - Write '1' to disable interrupt for EDSTOPPED event

pub fn ccaidle(&self) -> CCAIDLER[src]

Bit 17 - Write '1' to disable interrupt for CCAIDLE event

pub fn ccabusy(&self) -> CCABUSYR[src]

Bit 18 - Write '1' to disable interrupt for CCABUSY event

pub fn ccastopped(&self) -> CCASTOPPEDR[src]

Bit 19 - Write '1' to disable interrupt for CCASTOPPED event

pub fn rateboost(&self) -> RATEBOOSTR[src]

Bit 20 - Write '1' to disable interrupt for RATEBOOST event

pub fn txready(&self) -> TXREADYR[src]

Bit 21 - Write '1' to disable interrupt for TXREADY event

pub fn rxready(&self) -> RXREADYR[src]

Bit 22 - Write '1' to disable interrupt for RXREADY event

pub fn mhrmatch(&self) -> MHRMATCHR[src]

Bit 23 - Write '1' to disable interrupt for MHRMATCH event

pub fn phyend(&self) -> PHYENDR[src]

Bit 27 - Write '1' to disable interrupt for PHYEND event

Auto Trait Implementations

impl Send for R

impl Sync for R

Blanket Implementations

impl<T> From for T[src]

impl<T, U> TryFrom for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T, U> Into for T where
    U: From<T>, [src]

impl<T> Borrow for T where
    T: ?Sized, [src]

impl<T> BorrowMut for T where
    T: ?Sized, [src]

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Same for T

type Output = T

Should always be Self