Struct nrf52840_hal::target::spim0::iftiming::rxdelay::W

pub struct W { /* private fields */ }

Value to write to the register

Implementations

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register

pub fn rxdelay(&mut self) -> _RXDELAYW<'_>

Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.