Struct nrf52811_pac::radio::intenclr::W

pub struct W(_);

Register INTENCLR writer

Implementations

impl W

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Write ‘1’ to disable interrupt for event READY

pub fn address(&mut self) -> ADDRESS_W<'_>

Bit 1 - Write ‘1’ to disable interrupt for event ADDRESS

pub fn payload(&mut self) -> PAYLOAD_W<'_>

Bit 2 - Write ‘1’ to disable interrupt for event PAYLOAD

pub fn end(&mut self) -> END_W<'_>

Bit 3 - Write ‘1’ to disable interrupt for event END

pub fn disabled(&mut self) -> DISABLED_W<'_>

Bit 4 - Write ‘1’ to disable interrupt for event DISABLED

pub fn devmatch(&mut self) -> DEVMATCH_W<'_>

Bit 5 - Write ‘1’ to disable interrupt for event DEVMATCH

pub fn devmiss(&mut self) -> DEVMISS_W<'_>

Bit 6 - Write ‘1’ to disable interrupt for event DEVMISS

pub fn rssiend(&mut self) -> RSSIEND_W<'_>

Bit 7 - Write ‘1’ to disable interrupt for event RSSIEND

pub fn bcmatch(&mut self) -> BCMATCH_W<'_>

Bit 10 - Write ‘1’ to disable interrupt for event BCMATCH

pub fn crcok(&mut self) -> CRCOK_W<'_>

Bit 12 - Write ‘1’ to disable interrupt for event CRCOK

pub fn crcerror(&mut self) -> CRCERROR_W<'_>

Bit 13 - Write ‘1’ to disable interrupt for event CRCERROR

pub fn framestart(&mut self) -> FRAMESTART_W<'_>

Bit 14 - Write ‘1’ to disable interrupt for event FRAMESTART

pub fn edend(&mut self) -> EDEND_W<'_>

Bit 15 - Write ‘1’ to disable interrupt for event EDEND

pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>

Bit 16 - Write ‘1’ to disable interrupt for event EDSTOPPED

pub fn ccaidle(&mut self) -> CCAIDLE_W<'_>

Bit 17 - Write ‘1’ to disable interrupt for event CCAIDLE

pub fn ccabusy(&mut self) -> CCABUSY_W<'_>

Bit 18 - Write ‘1’ to disable interrupt for event CCABUSY

pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>

Bit 19 - Write ‘1’ to disable interrupt for event CCASTOPPED

pub fn rateboost(&mut self) -> RATEBOOST_W<'_>

Bit 20 - Write ‘1’ to disable interrupt for event RATEBOOST

pub fn txready(&mut self) -> TXREADY_W<'_>

Bit 21 - Write ‘1’ to disable interrupt for event TXREADY

pub fn rxready(&mut self) -> RXREADY_W<'_>

Bit 22 - Write ‘1’ to disable interrupt for event RXREADY

pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>

Bit 23 - Write ‘1’ to disable interrupt for event MHRMATCH

pub fn phyend(&mut self) -> PHYEND_W<'_>

Bit 27 - Write ‘1’ to disable interrupt for event PHYEND

pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>

Bit 28 - Write ‘1’ to disable interrupt for event CTEPRESENT

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INTENCLR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTENCLR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INTENCLR_SPEC>> for W

fn from(writer: W<INTENCLR_SPEC>) -> Self

Performs the conversion.