[−][src]Crate nrf51

Peripheral access API for NRF51 microcontrollers (generated using svd2rust v0.16.1)

You can find an overview of the API here.

Re-exports

pub use self::Interrupt as interrupt;

aar	Accelerated Address Resolver.
adc	Analog to digital converter.
amli	AHB Multi-Layer Interface.
ccm	AES CCM Mode Encryption.
clock	Clock control.
ecb	AES ECB Mode Encryption.
ficr	Factory Information Configuration.
generic	Common register and bit access and modify traits
gpio	General purpose input and output.
gpiote	GPIO tasks and events.
lpcomp	Low power comparator.
nvmc	Non Volatile Memory Controller.
power	Power Control.
ppi	PPI controller.
qdec	Rotary decoder.
radio	The radio.
rng	Random Number Generator.
rtc0	Real time counter 0.
spi0	SPI master 0.
spim1	SPI master with easyDMA 1.
spis1	SPI slave 1.
swi	SW Interrupts.
temp	Temperature Sensor.
timer0	Timer 0.
twi0	Two-wire interface master 0.
uart0	Universal Asynchronous Receiver/Transmitter.
uicr	User Information Configuration.
wdt	Watchdog Timer.

AAR	Accelerated Address Resolver.
ADC	Analog to digital converter.
AMLI	AHB Multi-Layer Interface.
CBP	Cache and branch predictor maintenance operations
CCM	AES CCM Mode Encryption.
CLOCK	Clock control.
CPUID	CPUID
CorePeripherals	Core peripherals
DCB	Debug Control Block
DWT	Data Watchpoint and Trace unit
ECB	AES ECB Mode Encryption.
FICR	Factory Information Configuration.
FPB	Flash Patch and Breakpoint unit
GPIO	General purpose input and output.
GPIOTE	GPIO tasks and events.
ITM	Instrumentation Trace Macrocell
LPCOMP	Low power comparator.
MPU	Memory Protection Unit
NVIC	Nested Vector Interrupt Controller
NVMC	Non Volatile Memory Controller.
POWER	Power Control.
PPI	PPI controller.
Peripherals	All the peripherals
QDEC	Rotary decoder.
RADIO	The radio.
RNG	Random Number Generator.
RTC0	Real time counter 0.
RTC1	Real time counter 1.
SCB	System Control Block
SPI0	SPI master 0.
SPI1	SPI master 1.
SPIM1	SPI master with easyDMA 1.
SPIS1	SPI slave 1.
SWI	SW Interrupts.
SYST	SysTick: System Timer
TEMP	Temperature Sensor.
TIMER0	Timer 0.
TIMER1	Timer 1.
TIMER2	Timer 2.
TPIU	Trace Port Interface Unit
TWI0	Two-wire interface master 0.
TWI1	Two-wire interface master 1.
UART0	Universal Asynchronous Receiver/Transmitter.
UICR	User Information Configuration.
WDT	Watchdog Timer.

Enumeration of all the interrupts

Number available in the NVIC for configuring priority

Attribute to declare an interrupt (AKA device-specific exception) handler