Struct msp432p401r::flctl::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 50 fields
pub flctl_power_stat: Reg<FLCTL_POWER_STAT_SPEC>,
pub flctl_bank0_rdctl: Reg<FLCTL_BANK0_RDCTL_SPEC>,
pub flctl_bank1_rdctl: Reg<FLCTL_BANK1_RDCTL_SPEC>,
pub flctl_rdbrst_ctlstat: Reg<FLCTL_RDBRST_CTLSTAT_SPEC>,
pub flctl_rdbrst_startaddr: Reg<FLCTL_RDBRST_STARTADDR_SPEC>,
pub flctl_rdbrst_len: Reg<FLCTL_RDBRST_LEN_SPEC>,
pub flctl_rdbrst_failaddr: Reg<FLCTL_RDBRST_FAILADDR_SPEC>,
pub flctl_rdbrst_failcnt: Reg<FLCTL_RDBRST_FAILCNT_SPEC>,
pub flctl_prg_ctlstat: Reg<FLCTL_PRG_CTLSTAT_SPEC>,
pub flctl_prgbrst_ctlstat: Reg<FLCTL_PRGBRST_CTLSTAT_SPEC>,
pub flctl_prgbrst_startaddr: Reg<FLCTL_PRGBRST_STARTADDR_SPEC>,
pub flctl_prgbrst_data0_0: Reg<FLCTL_PRGBRST_DATA0_0_SPEC>,
pub flctl_prgbrst_data0_1: Reg<FLCTL_PRGBRST_DATA0_1_SPEC>,
pub flctl_prgbrst_data0_2: Reg<FLCTL_PRGBRST_DATA0_2_SPEC>,
pub flctl_prgbrst_data0_3: Reg<FLCTL_PRGBRST_DATA0_3_SPEC>,
pub flctl_prgbrst_data1_0: Reg<FLCTL_PRGBRST_DATA1_0_SPEC>,
pub flctl_prgbrst_data1_1: Reg<FLCTL_PRGBRST_DATA1_1_SPEC>,
pub flctl_prgbrst_data1_2: Reg<FLCTL_PRGBRST_DATA1_2_SPEC>,
pub flctl_prgbrst_data1_3: Reg<FLCTL_PRGBRST_DATA1_3_SPEC>,
pub flctl_prgbrst_data2_0: Reg<FLCTL_PRGBRST_DATA2_0_SPEC>,
pub flctl_prgbrst_data2_1: Reg<FLCTL_PRGBRST_DATA2_1_SPEC>,
pub flctl_prgbrst_data2_2: Reg<FLCTL_PRGBRST_DATA2_2_SPEC>,
pub flctl_prgbrst_data2_3: Reg<FLCTL_PRGBRST_DATA2_3_SPEC>,
pub flctl_prgbrst_data3_0: Reg<FLCTL_PRGBRST_DATA3_0_SPEC>,
pub flctl_prgbrst_data3_1: Reg<FLCTL_PRGBRST_DATA3_1_SPEC>,
pub flctl_prgbrst_data3_2: Reg<FLCTL_PRGBRST_DATA3_2_SPEC>,
pub flctl_prgbrst_data3_3: Reg<FLCTL_PRGBRST_DATA3_3_SPEC>,
pub flctl_erase_ctlstat: Reg<FLCTL_ERASE_CTLSTAT_SPEC>,
pub flctl_erase_sectaddr: Reg<FLCTL_ERASE_SECTADDR_SPEC>,
pub flctl_bank0_info_weprot: Reg<FLCTL_BANK0_INFO_WEPROT_SPEC>,
pub flctl_bank0_main_weprot: Reg<FLCTL_BANK0_MAIN_WEPROT_SPEC>,
pub flctl_bank1_info_weprot: Reg<FLCTL_BANK1_INFO_WEPROT_SPEC>,
pub flctl_bank1_main_weprot: Reg<FLCTL_BANK1_MAIN_WEPROT_SPEC>,
pub flctl_bmrk_ctlstat: Reg<FLCTL_BMRK_CTLSTAT_SPEC>,
pub flctl_bmrk_ifetch: Reg<FLCTL_BMRK_IFETCH_SPEC>,
pub flctl_bmrk_dread: Reg<FLCTL_BMRK_DREAD_SPEC>,
pub flctl_bmrk_cmp: Reg<FLCTL_BMRK_CMP_SPEC>,
pub flctl_ifg: Reg<FLCTL_IFG_SPEC>,
pub flctl_ie: Reg<FLCTL_IE_SPEC>,
pub flctl_clrifg: Reg<FLCTL_CLRIFG_SPEC>,
pub flctl_setifg: Reg<FLCTL_SETIFG_SPEC>,
pub flctl_read_timctl: Reg<FLCTL_READ_TIMCTL_SPEC>,
pub flctl_readmargin_timctl: Reg<FLCTL_READMARGIN_TIMCTL_SPEC>,
pub flctl_prgver_timctl: Reg<FLCTL_PRGVER_TIMCTL_SPEC>,
pub flctl_ersver_timctl: Reg<FLCTL_ERSVER_TIMCTL_SPEC>,
pub flctl_lkgver_timctl: Reg<FLCTL_LKGVER_TIMCTL_SPEC>,
pub flctl_program_timctl: Reg<FLCTL_PROGRAM_TIMCTL_SPEC>,
pub flctl_erase_timctl: Reg<FLCTL_ERASE_TIMCTL_SPEC>,
pub flctl_masserase_timctl: Reg<FLCTL_MASSERASE_TIMCTL_SPEC>,
pub flctl_burstprg_timctl: Reg<FLCTL_BURSTPRG_TIMCTL_SPEC>,
/* private fields */
}
Expand description
Register block
Fields
flctl_power_stat: Reg<FLCTL_POWER_STAT_SPEC>
0x00 - Power Status Register
flctl_bank0_rdctl: Reg<FLCTL_BANK0_RDCTL_SPEC>
0x10 - Bank0 Read Control Register
flctl_bank1_rdctl: Reg<FLCTL_BANK1_RDCTL_SPEC>
0x14 - Bank1 Read Control Register
flctl_rdbrst_ctlstat: Reg<FLCTL_RDBRST_CTLSTAT_SPEC>
0x20 - Read Burst/Compare Control and Status Register
flctl_rdbrst_startaddr: Reg<FLCTL_RDBRST_STARTADDR_SPEC>
0x24 - Read Burst/Compare Start Address Register
flctl_rdbrst_len: Reg<FLCTL_RDBRST_LEN_SPEC>
0x28 - Read Burst/Compare Length Register
flctl_rdbrst_failaddr: Reg<FLCTL_RDBRST_FAILADDR_SPEC>
0x3c - Read Burst/Compare Fail Address Register
flctl_rdbrst_failcnt: Reg<FLCTL_RDBRST_FAILCNT_SPEC>
0x40 - Read Burst/Compare Fail Count Register
flctl_prg_ctlstat: Reg<FLCTL_PRG_CTLSTAT_SPEC>
0x50 - Program Control and Status Register
flctl_prgbrst_ctlstat: Reg<FLCTL_PRGBRST_CTLSTAT_SPEC>
0x54 - Program Burst Control and Status Register
flctl_prgbrst_startaddr: Reg<FLCTL_PRGBRST_STARTADDR_SPEC>
0x58 - Program Burst Start Address Register
flctl_prgbrst_data0_0: Reg<FLCTL_PRGBRST_DATA0_0_SPEC>
0x60 - Program Burst Data0 Register0
flctl_prgbrst_data0_1: Reg<FLCTL_PRGBRST_DATA0_1_SPEC>
0x64 - Program Burst Data0 Register1
flctl_prgbrst_data0_2: Reg<FLCTL_PRGBRST_DATA0_2_SPEC>
0x68 - Program Burst Data0 Register2
flctl_prgbrst_data0_3: Reg<FLCTL_PRGBRST_DATA0_3_SPEC>
0x6c - Program Burst Data0 Register3
flctl_prgbrst_data1_0: Reg<FLCTL_PRGBRST_DATA1_0_SPEC>
0x70 - Program Burst Data1 Register0
flctl_prgbrst_data1_1: Reg<FLCTL_PRGBRST_DATA1_1_SPEC>
0x74 - Program Burst Data1 Register1
flctl_prgbrst_data1_2: Reg<FLCTL_PRGBRST_DATA1_2_SPEC>
0x78 - Program Burst Data1 Register2
flctl_prgbrst_data1_3: Reg<FLCTL_PRGBRST_DATA1_3_SPEC>
0x7c - Program Burst Data1 Register3
flctl_prgbrst_data2_0: Reg<FLCTL_PRGBRST_DATA2_0_SPEC>
0x80 - Program Burst Data2 Register0
flctl_prgbrst_data2_1: Reg<FLCTL_PRGBRST_DATA2_1_SPEC>
0x84 - Program Burst Data2 Register1
flctl_prgbrst_data2_2: Reg<FLCTL_PRGBRST_DATA2_2_SPEC>
0x88 - Program Burst Data2 Register2
flctl_prgbrst_data2_3: Reg<FLCTL_PRGBRST_DATA2_3_SPEC>
0x8c - Program Burst Data2 Register3
flctl_prgbrst_data3_0: Reg<FLCTL_PRGBRST_DATA3_0_SPEC>
0x90 - Program Burst Data3 Register0
flctl_prgbrst_data3_1: Reg<FLCTL_PRGBRST_DATA3_1_SPEC>
0x94 - Program Burst Data3 Register1
flctl_prgbrst_data3_2: Reg<FLCTL_PRGBRST_DATA3_2_SPEC>
0x98 - Program Burst Data3 Register2
flctl_prgbrst_data3_3: Reg<FLCTL_PRGBRST_DATA3_3_SPEC>
0x9c - Program Burst Data3 Register3
flctl_erase_ctlstat: Reg<FLCTL_ERASE_CTLSTAT_SPEC>
0xa0 - Erase Control and Status Register
flctl_erase_sectaddr: Reg<FLCTL_ERASE_SECTADDR_SPEC>
0xa4 - Erase Sector Address Register
flctl_bank0_info_weprot: Reg<FLCTL_BANK0_INFO_WEPROT_SPEC>
0xb0 - Information Memory Bank0 Write/Erase Protection Register
flctl_bank0_main_weprot: Reg<FLCTL_BANK0_MAIN_WEPROT_SPEC>
0xb4 - Main Memory Bank0 Write/Erase Protection Register
flctl_bank1_info_weprot: Reg<FLCTL_BANK1_INFO_WEPROT_SPEC>
0xc0 - Information Memory Bank1 Write/Erase Protection Register
flctl_bank1_main_weprot: Reg<FLCTL_BANK1_MAIN_WEPROT_SPEC>
0xc4 - Main Memory Bank1 Write/Erase Protection Register
flctl_bmrk_ctlstat: Reg<FLCTL_BMRK_CTLSTAT_SPEC>
0xd0 - Benchmark Control and Status Register
flctl_bmrk_ifetch: Reg<FLCTL_BMRK_IFETCH_SPEC>
0xd4 - Benchmark Instruction Fetch Count Register
flctl_bmrk_dread: Reg<FLCTL_BMRK_DREAD_SPEC>
0xd8 - Benchmark Data Read Count Register
flctl_bmrk_cmp: Reg<FLCTL_BMRK_CMP_SPEC>
0xdc - Benchmark Count Compare Register
flctl_ifg: Reg<FLCTL_IFG_SPEC>
0xf0 - Interrupt Flag Register
flctl_ie: Reg<FLCTL_IE_SPEC>
0xf4 - Interrupt Enable Register
flctl_clrifg: Reg<FLCTL_CLRIFG_SPEC>
0xf8 - Clear Interrupt Flag Register
flctl_setifg: Reg<FLCTL_SETIFG_SPEC>
0xfc - Set Interrupt Flag Register
flctl_read_timctl: Reg<FLCTL_READ_TIMCTL_SPEC>
0x100 - Read Timing Control Register
flctl_readmargin_timctl: Reg<FLCTL_READMARGIN_TIMCTL_SPEC>
0x104 - Read Margin Timing Control Register
flctl_prgver_timctl: Reg<FLCTL_PRGVER_TIMCTL_SPEC>
0x108 - Program Verify Timing Control Register
flctl_ersver_timctl: Reg<FLCTL_ERSVER_TIMCTL_SPEC>
0x10c - Erase Verify Timing Control Register
flctl_lkgver_timctl: Reg<FLCTL_LKGVER_TIMCTL_SPEC>
0x110 - Leakage Verify Timing Control Register
flctl_program_timctl: Reg<FLCTL_PROGRAM_TIMCTL_SPEC>
0x114 - Program Timing Control Register
flctl_erase_timctl: Reg<FLCTL_ERASE_TIMCTL_SPEC>
0x118 - Erase Timing Control Register
flctl_masserase_timctl: Reg<FLCTL_MASSERASE_TIMCTL_SPEC>
0x11c - Mass Erase Timing Control Register
flctl_burstprg_timctl: Reg<FLCTL_BURSTPRG_TIMCTL_SPEC>
0x120 - Burst Program Timing Control Register
Auto Trait Implementations
impl !RefUnwindSafe for RegisterBlock
impl Send for RegisterBlock
impl !Sync for RegisterBlock
impl Unpin for RegisterBlock
impl UnwindSafe for RegisterBlock
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more