Struct msp432p401r::dma::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub dma_device_cfg: Reg<DMA_DEVICE_CFG_SPEC>,
    pub dma_sw_chtrig: Reg<DMA_SW_CHTRIG_SPEC>,
    pub dma_ch_srccfg: [Reg<DMA_CH_SRCCFG_SPEC>; 32],
    pub dma_int1_srccfg: Reg<DMA_INT1_SRCCFG_SPEC>,
    pub dma_int2_srccfg: Reg<DMA_INT2_SRCCFG_SPEC>,
    pub dma_int3_srccfg: Reg<DMA_INT3_SRCCFG_SPEC>,
    pub dma_int0_srcflg: Reg<DMA_INT0_SRCFLG_SPEC>,
    pub dma_int0_clrflg: Reg<DMA_INT0_CLRFLG_SPEC>,
    pub dma_stat: Reg<DMA_STAT_SPEC>,
    pub dma_cfg: Reg<DMA_CFG_SPEC>,
    pub dma_ctlbase: Reg<DMA_CTLBASE_SPEC>,
    pub dma_altbase: Reg<DMA_ALTBASE_SPEC>,
    pub dma_waitstat: Reg<DMA_WAITSTAT_SPEC>,
    pub dma_swreq: Reg<DMA_SWREQ_SPEC>,
    pub dma_useburstset: Reg<DMA_USEBURSTSET_SPEC>,
    pub dma_useburstclr: Reg<DMA_USEBURSTCLR_SPEC>,
    pub dma_reqmaskset: Reg<DMA_REQMASKSET_SPEC>,
    pub dma_reqmaskclr: Reg<DMA_REQMASKCLR_SPEC>,
    pub dma_enaset: Reg<DMA_ENASET_SPEC>,
    pub dma_enaclr: Reg<DMA_ENACLR_SPEC>,
    pub dma_altset: Reg<DMA_ALTSET_SPEC>,
    pub dma_altclr: Reg<DMA_ALTCLR_SPEC>,
    pub dma_prioset: Reg<DMA_PRIOSET_SPEC>,
    pub dma_prioclr: Reg<DMA_PRIOCLR_SPEC>,
    pub dma_errclr: Reg<DMA_ERRCLR_SPEC>,
    // some fields omitted
}

Register block

Fields

dma_device_cfg: Reg<DMA_DEVICE_CFG_SPEC>

0x00 - Device Configuration Status

dma_sw_chtrig: Reg<DMA_SW_CHTRIG_SPEC>

0x04 - Software Channel Trigger Register

dma_ch_srccfg: [Reg<DMA_CH_SRCCFG_SPEC>; 32]

0x10 - Channel n Source Configuration Register

dma_int1_srccfg: Reg<DMA_INT1_SRCCFG_SPEC>

0x100 - Interrupt 1 Source Channel Configuration

dma_int2_srccfg: Reg<DMA_INT2_SRCCFG_SPEC>

0x104 - Interrupt 2 Source Channel Configuration Register

dma_int3_srccfg: Reg<DMA_INT3_SRCCFG_SPEC>

0x108 - Interrupt 3 Source Channel Configuration Register

dma_int0_srcflg: Reg<DMA_INT0_SRCFLG_SPEC>

0x110 - Interrupt 0 Source Channel Flag Register

dma_int0_clrflg: Reg<DMA_INT0_CLRFLG_SPEC>

0x114 - Interrupt 0 Source Channel Clear Flag Register

dma_stat: Reg<DMA_STAT_SPEC>

0x1000 - Status Register

dma_cfg: Reg<DMA_CFG_SPEC>

0x1004 - Configuration Register

dma_ctlbase: Reg<DMA_CTLBASE_SPEC>

0x1008 - Channel Control Data Base Pointer Register

dma_altbase: Reg<DMA_ALTBASE_SPEC>

0x100c - Channel Alternate Control Data Base Pointer Register

dma_waitstat: Reg<DMA_WAITSTAT_SPEC>

0x1010 - Channel Wait on Request Status Register

dma_swreq: Reg<DMA_SWREQ_SPEC>

0x1014 - Channel Software Request Register

dma_useburstset: Reg<DMA_USEBURSTSET_SPEC>

0x1018 - Channel Useburst Set Register

dma_useburstclr: Reg<DMA_USEBURSTCLR_SPEC>

0x101c - Channel Useburst Clear Register

dma_reqmaskset: Reg<DMA_REQMASKSET_SPEC>

0x1020 - Channel Request Mask Set Register

dma_reqmaskclr: Reg<DMA_REQMASKCLR_SPEC>

0x1024 - Channel Request Mask Clear Register

dma_enaset: Reg<DMA_ENASET_SPEC>

0x1028 - Channel Enable Set Register

dma_enaclr: Reg<DMA_ENACLR_SPEC>

0x102c - Channel Enable Clear Register

dma_altset: Reg<DMA_ALTSET_SPEC>

0x1030 - Channel Primary-Alternate Set Register

dma_altclr: Reg<DMA_ALTCLR_SPEC>

0x1034 - Channel Primary-Alternate Clear Register

dma_prioset: Reg<DMA_PRIOSET_SPEC>

0x1038 - Channel Priority Set Register

dma_prioclr: Reg<DMA_PRIOCLR_SPEC>

0x103c - Channel Priority Clear Register

dma_errclr: Reg<DMA_ERRCLR_SPEC>

0x104c - Bus Error Clear Register

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