NMI Control and Status Register
| CS_FLG_R | Field CS_FLG reader - CS interrupt was the source of NMI
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| CS_SRC_R | Field CS_SRC reader - CS interrupt as a source of NMI
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| CS_SRC_W | Field CS_SRC writer - CS interrupt as a source of NMI
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| PCM_FLG_R | Field PCM_FLG reader - PCM interrupt was the source of NMI
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| PCM_SRC_R | Field PCM_SRC reader - PCM interrupt as a source of NMI
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| PCM_SRC_W | Field PCM_SRC writer - PCM interrupt as a source of NMI
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| PIN_FLG_R | Field PIN_FLG reader - RSTn/NMI pin was the source of NMI
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| PIN_FLG_W | Field PIN_FLG writer - RSTn/NMI pin was the source of NMI
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| PIN_SRC_R | Field PIN_SRC reader - RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes.
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| PIN_SRC_W | Field PIN_SRC writer - RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes.
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| PSS_FLG_R | Field PSS_FLG reader - PSS interrupt was the source of NMI
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| PSS_SRC_R | Field PSS_SRC reader - PSS interrupt as a source of NMI
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| PSS_SRC_W | Field PSS_SRC writer - PSS interrupt as a source of NMI
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| R | Register SYS_NMI_CTLSTAT reader
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| SYS_NMI_CTLSTAT_SPEC | NMI Control and Status Register
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| W | Register SYS_NMI_CTLSTAT writer
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| CS_FLG_A | CS interrupt was the source of NMI
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| CS_SRC_A | CS interrupt as a source of NMI
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| PCM_FLG_A | PCM interrupt was the source of NMI
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| PCM_SRC_A | PCM interrupt as a source of NMI
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| PIN_FLG_A | RSTn/NMI pin was the source of NMI
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| PIN_SRC_A | RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes.
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| PSS_FLG_A | PSS interrupt was the source of NMI
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| PSS_SRC_A | PSS interrupt as a source of NMI
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