Struct msp432p401r::dma::dma_sw_chtrig::R[][src]

pub struct R(_);

Register DMA_SW_CHTRIG reader

Implementations

impl R[src]

pub fn ch0(&self) -> CH0_R[src]

Bit 0 - Write 1, triggers DMA_CHANNEL0

pub fn ch1(&self) -> CH1_R[src]

Bit 1 - Write 1, triggers DMA_CHANNEL1

pub fn ch2(&self) -> CH2_R[src]

Bit 2 - Write 1, triggers DMA_CHANNEL2

pub fn ch3(&self) -> CH3_R[src]

Bit 3 - Write 1, triggers DMA_CHANNEL3

pub fn ch4(&self) -> CH4_R[src]

Bit 4 - Write 1, triggers DMA_CHANNEL4

pub fn ch5(&self) -> CH5_R[src]

Bit 5 - Write 1, triggers DMA_CHANNEL5

pub fn ch6(&self) -> CH6_R[src]

Bit 6 - Write 1, triggers DMA_CHANNEL6

pub fn ch7(&self) -> CH7_R[src]

Bit 7 - Write 1, triggers DMA_CHANNEL7

pub fn ch8(&self) -> CH8_R[src]

Bit 8 - Write 1, triggers DMA_CHANNEL8

pub fn ch9(&self) -> CH9_R[src]

Bit 9 - Write 1, triggers DMA_CHANNEL9

pub fn ch10(&self) -> CH10_R[src]

Bit 10 - Write 1, triggers DMA_CHANNEL10

pub fn ch11(&self) -> CH11_R[src]

Bit 11 - Write 1, triggers DMA_CHANNEL11

pub fn ch12(&self) -> CH12_R[src]

Bit 12 - Write 1, triggers DMA_CHANNEL12

pub fn ch13(&self) -> CH13_R[src]

Bit 13 - Write 1, triggers DMA_CHANNEL13

pub fn ch14(&self) -> CH14_R[src]

Bit 14 - Write 1, triggers DMA_CHANNEL14

pub fn ch15(&self) -> CH15_R[src]

Bit 15 - Write 1, triggers DMA_CHANNEL15

pub fn ch16(&self) -> CH16_R[src]

Bit 16 - Write 1, triggers DMA_CHANNEL16

pub fn ch17(&self) -> CH17_R[src]

Bit 17 - Write 1, triggers DMA_CHANNEL17

pub fn ch18(&self) -> CH18_R[src]

Bit 18 - Write 1, triggers DMA_CHANNEL18

pub fn ch19(&self) -> CH19_R[src]

Bit 19 - Write 1, triggers DMA_CHANNEL19

pub fn ch20(&self) -> CH20_R[src]

Bit 20 - Write 1, triggers DMA_CHANNEL20

pub fn ch21(&self) -> CH21_R[src]

Bit 21 - Write 1, triggers DMA_CHANNEL21

pub fn ch22(&self) -> CH22_R[src]

Bit 22 - Write 1, triggers DMA_CHANNEL22

pub fn ch23(&self) -> CH23_R[src]

Bit 23 - Write 1, triggers DMA_CHANNEL23

pub fn ch24(&self) -> CH24_R[src]

Bit 24 - Write 1, triggers DMA_CHANNEL24

pub fn ch25(&self) -> CH25_R[src]

Bit 25 - Write 1, triggers DMA_CHANNEL25

pub fn ch26(&self) -> CH26_R[src]

Bit 26 - Write 1, triggers DMA_CHANNEL26

pub fn ch27(&self) -> CH27_R[src]

Bit 27 - Write 1, triggers DMA_CHANNEL27

pub fn ch28(&self) -> CH28_R[src]

Bit 28 - Write 1, triggers DMA_CHANNEL28

pub fn ch29(&self) -> CH29_R[src]

Bit 29 - Write 1, triggers DMA_CHANNEL29

pub fn ch30(&self) -> CH30_R[src]

Bit 30 - Write 1, triggers DMA_CHANNEL30

pub fn ch31(&self) -> CH31_R[src]

Bit 31 - Write 1, triggers DMA_CHANNEL31

Methods from Deref<Target = R<DMA_SW_CHTRIG_SPEC>>

pub fn bits(&self) -> REG::Ux[src]

Reads raw bits from register.

Trait Implementations

impl Deref for R[src]

type Target = R<DMA_SW_CHTRIG_SPEC>

The resulting type after dereferencing.

impl From<R<DMA_SW_CHTRIG_SPEC>> for R[src]

Auto Trait Implementations

impl Send for R

impl Sync for R

impl Unpin for R

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.