Struct msp432p401r::dio::RegisterBlock[][src]

#[repr(C)]pub struct RegisterBlock {
    pub pain: Reg<PAIN_SPEC>,
    pub paout: Reg<PAOUT_SPEC>,
    pub padir: Reg<PADIR_SPEC>,
    pub paren: Reg<PAREN_SPEC>,
    pub pads: Reg<PADS_SPEC>,
    pub pasel0: Reg<PASEL0_SPEC>,
    pub pasel1: Reg<PASEL1_SPEC>,
    pub p1iv: Reg<P1IV_SPEC>,
    pub paselc: Reg<PASELC_SPEC>,
    pub paies: Reg<PAIES_SPEC>,
    pub paie: Reg<PAIE_SPEC>,
    pub paifg: Reg<PAIFG_SPEC>,
    pub p2iv: Reg<P2IV_SPEC>,
    pub pbin: Reg<PBIN_SPEC>,
    pub pbout: Reg<PBOUT_SPEC>,
    pub pbdir: Reg<PBDIR_SPEC>,
    pub pbren: Reg<PBREN_SPEC>,
    pub pbds: Reg<PBDS_SPEC>,
    pub pbsel0: Reg<PBSEL0_SPEC>,
    pub pbsel1: Reg<PBSEL1_SPEC>,
    pub p3iv: Reg<P3IV_SPEC>,
    pub pbselc: Reg<PBSELC_SPEC>,
    pub pbies: Reg<PBIES_SPEC>,
    pub pbie: Reg<PBIE_SPEC>,
    pub pbifg: Reg<PBIFG_SPEC>,
    pub p4iv: Reg<P4IV_SPEC>,
    pub pcin: Reg<PCIN_SPEC>,
    pub pcout: Reg<PCOUT_SPEC>,
    pub pcdir: Reg<PCDIR_SPEC>,
    pub pcren: Reg<PCREN_SPEC>,
    pub pcds: Reg<PCDS_SPEC>,
    pub pcsel0: Reg<PCSEL0_SPEC>,
    pub pcsel1: Reg<PCSEL1_SPEC>,
    pub p5iv: Reg<P5IV_SPEC>,
    pub pcselc: Reg<PCSELC_SPEC>,
    pub pcies: Reg<PCIES_SPEC>,
    pub pcie: Reg<PCIE_SPEC>,
    pub pcifg: Reg<PCIFG_SPEC>,
    pub p6iv: Reg<P6IV_SPEC>,
    pub pdin: Reg<PDIN_SPEC>,
    pub pdout: Reg<PDOUT_SPEC>,
    pub pddir: Reg<PDDIR_SPEC>,
    pub pdren: Reg<PDREN_SPEC>,
    pub pdds: Reg<PDDS_SPEC>,
    pub pdsel0: Reg<PDSEL0_SPEC>,
    pub pdsel1: Reg<PDSEL1_SPEC>,
    pub p7iv: Reg<P7IV_SPEC>,
    pub pdselc: Reg<PDSELC_SPEC>,
    pub pdies: Reg<PDIES_SPEC>,
    pub pdie: Reg<PDIE_SPEC>,
    pub pdifg: Reg<PDIFG_SPEC>,
    pub p8iv: Reg<P8IV_SPEC>,
    pub pein: Reg<PEIN_SPEC>,
    pub peout: Reg<PEOUT_SPEC>,
    pub pedir: Reg<PEDIR_SPEC>,
    pub peren: Reg<PEREN_SPEC>,
    pub peds: Reg<PEDS_SPEC>,
    pub pesel0: Reg<PESEL0_SPEC>,
    pub pesel1: Reg<PESEL1_SPEC>,
    pub p9iv: Reg<P9IV_SPEC>,
    pub peselc: Reg<PESELC_SPEC>,
    pub peies: Reg<PEIES_SPEC>,
    pub peie: Reg<PEIE_SPEC>,
    pub peifg: Reg<PEIFG_SPEC>,
    pub p10iv: Reg<P10IV_SPEC>,
    pub pjin: Reg<PJIN_SPEC>,
    pub pjout: Reg<PJOUT_SPEC>,
    pub pjdir: Reg<PJDIR_SPEC>,
    pub pjren: Reg<PJREN_SPEC>,
    pub pjds: Reg<PJDS_SPEC>,
    pub pjsel0: Reg<PJSEL0_SPEC>,
    pub pjsel1: Reg<PJSEL1_SPEC>,
    pub pjselc: Reg<PJSELC_SPEC>,
    // some fields omitted
}

Register block

Fields

pain: Reg<PAIN_SPEC>

0x00 - Port A Input

paout: Reg<PAOUT_SPEC>

0x02 - Port A Output

padir: Reg<PADIR_SPEC>

0x04 - Port A Direction

paren: Reg<PAREN_SPEC>

0x06 - Port A Resistor Enable

pads: Reg<PADS_SPEC>

0x08 - Port A Drive Strength

pasel0: Reg<PASEL0_SPEC>

0x0a - Port A Select 0

pasel1: Reg<PASEL1_SPEC>

0x0c - Port A Select 1

p1iv: Reg<P1IV_SPEC>

0x0e - Port 1 Interrupt Vector Register

paselc: Reg<PASELC_SPEC>

0x16 - Port A Complement Select

paies: Reg<PAIES_SPEC>

0x18 - Port A Interrupt Edge Select

paie: Reg<PAIE_SPEC>

0x1a - Port A Interrupt Enable

paifg: Reg<PAIFG_SPEC>

0x1c - Port A Interrupt Flag

p2iv: Reg<P2IV_SPEC>

0x1e - Port 2 Interrupt Vector Register

pbin: Reg<PBIN_SPEC>

0x20 - Port B Input

pbout: Reg<PBOUT_SPEC>

0x22 - Port B Output

pbdir: Reg<PBDIR_SPEC>

0x24 - Port B Direction

pbren: Reg<PBREN_SPEC>

0x26 - Port B Resistor Enable

pbds: Reg<PBDS_SPEC>

0x28 - Port B Drive Strength

pbsel0: Reg<PBSEL0_SPEC>

0x2a - Port B Select 0

pbsel1: Reg<PBSEL1_SPEC>

0x2c - Port B Select 1

p3iv: Reg<P3IV_SPEC>

0x2e - Port 3 Interrupt Vector Register

pbselc: Reg<PBSELC_SPEC>

0x36 - Port B Complement Select

pbies: Reg<PBIES_SPEC>

0x38 - Port B Interrupt Edge Select

pbie: Reg<PBIE_SPEC>

0x3a - Port B Interrupt Enable

pbifg: Reg<PBIFG_SPEC>

0x3c - Port B Interrupt Flag

p4iv: Reg<P4IV_SPEC>

0x3e - Port 4 Interrupt Vector Register

pcin: Reg<PCIN_SPEC>

0x40 - Port C Input

pcout: Reg<PCOUT_SPEC>

0x42 - Port C Output

pcdir: Reg<PCDIR_SPEC>

0x44 - Port C Direction

pcren: Reg<PCREN_SPEC>

0x46 - Port C Resistor Enable

pcds: Reg<PCDS_SPEC>

0x48 - Port C Drive Strength

pcsel0: Reg<PCSEL0_SPEC>

0x4a - Port C Select 0

pcsel1: Reg<PCSEL1_SPEC>

0x4c - Port C Select 1

p5iv: Reg<P5IV_SPEC>

0x4e - Port 5 Interrupt Vector Register

pcselc: Reg<PCSELC_SPEC>

0x56 - Port C Complement Select

pcies: Reg<PCIES_SPEC>

0x58 - Port C Interrupt Edge Select

pcie: Reg<PCIE_SPEC>

0x5a - Port C Interrupt Enable

pcifg: Reg<PCIFG_SPEC>

0x5c - Port C Interrupt Flag

p6iv: Reg<P6IV_SPEC>

0x5e - Port 6 Interrupt Vector Register

pdin: Reg<PDIN_SPEC>

0x60 - Port D Input

pdout: Reg<PDOUT_SPEC>

0x62 - Port D Output

pddir: Reg<PDDIR_SPEC>

0x64 - Port D Direction

pdren: Reg<PDREN_SPEC>

0x66 - Port D Resistor Enable

pdds: Reg<PDDS_SPEC>

0x68 - Port D Drive Strength

pdsel0: Reg<PDSEL0_SPEC>

0x6a - Port D Select 0

pdsel1: Reg<PDSEL1_SPEC>

0x6c - Port D Select 1

p7iv: Reg<P7IV_SPEC>

0x6e - Port 7 Interrupt Vector Register

pdselc: Reg<PDSELC_SPEC>

0x76 - Port D Complement Select

pdies: Reg<PDIES_SPEC>

0x78 - Port D Interrupt Edge Select

pdie: Reg<PDIE_SPEC>

0x7a - Port D Interrupt Enable

pdifg: Reg<PDIFG_SPEC>

0x7c - Port D Interrupt Flag

p8iv: Reg<P8IV_SPEC>

0x7e - Port 8 Interrupt Vector Register

pein: Reg<PEIN_SPEC>

0x80 - Port E Input

peout: Reg<PEOUT_SPEC>

0x82 - Port E Output

pedir: Reg<PEDIR_SPEC>

0x84 - Port E Direction

peren: Reg<PEREN_SPEC>

0x86 - Port E Resistor Enable

peds: Reg<PEDS_SPEC>

0x88 - Port E Drive Strength

pesel0: Reg<PESEL0_SPEC>

0x8a - Port E Select 0

pesel1: Reg<PESEL1_SPEC>

0x8c - Port E Select 1

p9iv: Reg<P9IV_SPEC>

0x8e - Port 9 Interrupt Vector Register

peselc: Reg<PESELC_SPEC>

0x96 - Port E Complement Select

peies: Reg<PEIES_SPEC>

0x98 - Port E Interrupt Edge Select

peie: Reg<PEIE_SPEC>

0x9a - Port E Interrupt Enable

peifg: Reg<PEIFG_SPEC>

0x9c - Port E Interrupt Flag

p10iv: Reg<P10IV_SPEC>

0x9e - Port 10 Interrupt Vector Register

pjin: Reg<PJIN_SPEC>

0x120 - Port J Input

pjout: Reg<PJOUT_SPEC>

0x122 - Port J Output

pjdir: Reg<PJDIR_SPEC>

0x124 - Port J Direction

pjren: Reg<PJREN_SPEC>

0x126 - Port J Resistor Enable

pjds: Reg<PJDS_SPEC>

0x128 - Port J Drive Strength

pjsel0: Reg<PJSEL0_SPEC>

0x12a - Port J Select 0

pjsel1: Reg<PJSEL1_SPEC>

0x12c - Port J Select 1

pjselc: Reg<PJSELC_SPEC>

0x136 - Port J Complement Select

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