Expand description

Port 1/2

Modules

Port 1 Direction

Port 1 Interrupt Enable

Port 1 Interrupt Edge Select

Port 1 Interrupt Flag

Port 1 Input

Port 1 Output

Port 1 Resistor Enable

Port 1 Selection

Port 1 Selection 2

Port 2 Direction

Port 2 Interrupt Enable

Port 2 Interrupt Edge Select

Port 2 Interrupt Flag

Port 2 Input

Port 2 Output

Port 2 Resistor Enable

Port 2 Selection

Port 2 Selection 2

Structs

Register block

Type Definitions

P1DIR (rw) register accessor: an alias for Reg<P1DIR_SPEC>

P1IE (rw) register accessor: an alias for Reg<P1IE_SPEC>

P1IES (rw) register accessor: an alias for Reg<P1IES_SPEC>

P1IFG (rw) register accessor: an alias for Reg<P1IFG_SPEC>

P1IN (rw) register accessor: an alias for Reg<P1IN_SPEC>

P1OUT (rw) register accessor: an alias for Reg<P1OUT_SPEC>

P1REN (rw) register accessor: an alias for Reg<P1REN_SPEC>

P1SEL (rw) register accessor: an alias for Reg<P1SEL_SPEC>

P1SEL2 (rw) register accessor: an alias for Reg<P1SEL2_SPEC>

P2DIR (rw) register accessor: an alias for Reg<P2DIR_SPEC>

P2IE (rw) register accessor: an alias for Reg<P2IE_SPEC>

P2IES (rw) register accessor: an alias for Reg<P2IES_SPEC>

P2IFG (rw) register accessor: an alias for Reg<P2IFG_SPEC>

P2IN (rw) register accessor: an alias for Reg<P2IN_SPEC>

P2OUT (rw) register accessor: an alias for Reg<P2OUT_SPEC>

P2REN (rw) register accessor: an alias for Reg<P2REN_SPEC>

P2SEL (rw) register accessor: an alias for Reg<P2SEL_SPEC>

P2SEL2 (rw) register accessor: an alias for Reg<P2SEL2_SPEC>