1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230

#[doc = "Register `UCB0CTL1` reader"]
pub struct R(crate::R<UCB0CTL1_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<UCB0CTL1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<UCB0CTL1_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<UCB0CTL1_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `UCB0CTL1` writer"]
pub struct W(crate::W<UCB0CTL1_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<UCB0CTL1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<UCB0CTL1_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<UCB0CTL1_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `UCSWRST` reader - USCI Software Reset"]
pub type UCSWRST_R = crate::BitReader<bool>;
#[doc = "Field `UCSWRST` writer - USCI Software Reset"]
pub type UCSWRST_W<'a, const O: u8> =
    crate::BitWriter<'a, u8, UCB0CTL1_SPEC, bool, O>;
#[doc = "Field `UCTXSTT` reader - Transmit START"]
pub type UCTXSTT_R = crate::BitReader<bool>;
#[doc = "Field `UCTXSTT` writer - Transmit START"]
pub type UCTXSTT_W<'a, const O: u8> =
    crate::BitWriter<'a, u8, UCB0CTL1_SPEC, bool, O>;
#[doc = "Field `UCTXSTP` reader - Transmit STOP"]
pub type UCTXSTP_R = crate::BitReader<bool>;
#[doc = "Field `UCTXSTP` writer - Transmit STOP"]
pub type UCTXSTP_W<'a, const O: u8> =
    crate::BitWriter<'a, u8, UCB0CTL1_SPEC, bool, O>;
#[doc = "Field `UCTXNACK` reader - Transmit NACK"]
pub type UCTXNACK_R = crate::BitReader<bool>;
#[doc = "Field `UCTXNACK` writer - Transmit NACK"]
pub type UCTXNACK_W<'a, const O: u8> =
    crate::BitWriter<'a, u8, UCB0CTL1_SPEC, bool, O>;
#[doc = "Field `UCTR` reader - Transmit/Receive Select/Flag"]
pub type UCTR_R = crate::BitReader<bool>;
#[doc = "Field `UCTR` writer - Transmit/Receive Select/Flag"]
pub type UCTR_W<'a, const O: u8> =
    crate::BitWriter<'a, u8, UCB0CTL1_SPEC, bool, O>;
#[doc = "Field `UCSSEL` reader - USCI 1 Clock Source Select 1"]
pub type UCSSEL_R = crate::FieldReader<u8, UCSSEL_A>;
#[doc = "USCI 1 Clock Source Select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum UCSSEL_A {
    #[doc = "0: USCI 0 Clock Source: 0"]
    UCSSEL_0 = 0,
    #[doc = "1: USCI 0 Clock Source: 1"]
    UCSSEL_1 = 1,
    #[doc = "2: USCI 0 Clock Source: 2"]
    UCSSEL_2 = 2,
    #[doc = "3: USCI 0 Clock Source: 3"]
    UCSSEL_3 = 3,
}
impl From<UCSSEL_A> for u8 {
    #[inline(always)]
    fn from(variant: UCSSEL_A) -> Self {
        variant as _
    }
}
impl UCSSEL_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> UCSSEL_A {
        match self.bits {
            0 => UCSSEL_A::UCSSEL_0,
            1 => UCSSEL_A::UCSSEL_1,
            2 => UCSSEL_A::UCSSEL_2,
            3 => UCSSEL_A::UCSSEL_3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `UCSSEL_0`"]
    #[inline(always)]
    pub fn is_ucssel_0(&self) -> bool {
        *self == UCSSEL_A::UCSSEL_0
    }
    #[doc = "Checks if the value of the field is `UCSSEL_1`"]
    #[inline(always)]
    pub fn is_ucssel_1(&self) -> bool {
        *self == UCSSEL_A::UCSSEL_1
    }
    #[doc = "Checks if the value of the field is `UCSSEL_2`"]
    #[inline(always)]
    pub fn is_ucssel_2(&self) -> bool {
        *self == UCSSEL_A::UCSSEL_2
    }
    #[doc = "Checks if the value of the field is `UCSSEL_3`"]
    #[inline(always)]
    pub fn is_ucssel_3(&self) -> bool {
        *self == UCSSEL_A::UCSSEL_3
    }
}
#[doc = "Field `UCSSEL` writer - USCI 1 Clock Source Select 1"]
pub type UCSSEL_W<'a, const O: u8> =
    crate::FieldWriterSafe<'a, u8, UCB0CTL1_SPEC, u8, UCSSEL_A, 2, O>;
impl<'a, const O: u8> UCSSEL_W<'a, O> {
    #[doc = "USCI 0 Clock Source: 0"]
    #[inline(always)]
    pub fn ucssel_0(self) -> &'a mut W {
        self.variant(UCSSEL_A::UCSSEL_0)
    }
    #[doc = "USCI 0 Clock Source: 1"]
    #[inline(always)]
    pub fn ucssel_1(self) -> &'a mut W {
        self.variant(UCSSEL_A::UCSSEL_1)
    }
    #[doc = "USCI 0 Clock Source: 2"]
    #[inline(always)]
    pub fn ucssel_2(self) -> &'a mut W {
        self.variant(UCSSEL_A::UCSSEL_2)
    }
    #[doc = "USCI 0 Clock Source: 3"]
    #[inline(always)]
    pub fn ucssel_3(self) -> &'a mut W {
        self.variant(UCSSEL_A::UCSSEL_3)
    }
}
impl R {
    #[doc = "Bit 0 - USCI Software Reset"]
    #[inline(always)]
    pub fn ucswrst(&self) -> UCSWRST_R {
        UCSWRST_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Transmit START"]
    #[inline(always)]
    pub fn uctxstt(&self) -> UCTXSTT_R {
        UCTXSTT_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Transmit STOP"]
    #[inline(always)]
    pub fn uctxstp(&self) -> UCTXSTP_R {
        UCTXSTP_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Transmit NACK"]
    #[inline(always)]
    pub fn uctxnack(&self) -> UCTXNACK_R {
        UCTXNACK_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Transmit/Receive Select/Flag"]
    #[inline(always)]
    pub fn uctr(&self) -> UCTR_R {
        UCTR_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bits 6:7 - USCI 1 Clock Source Select 1"]
    #[inline(always)]
    pub fn ucssel(&self) -> UCSSEL_R {
        UCSSEL_R::new(((self.bits >> 6) & 3) as u8)
    }
}
impl W {
    #[doc = "Bit 0 - USCI Software Reset"]
    #[inline(always)]
    pub fn ucswrst(&mut self) -> UCSWRST_W<0> {
        UCSWRST_W::new(self)
    }
    #[doc = "Bit 1 - Transmit START"]
    #[inline(always)]
    pub fn uctxstt(&mut self) -> UCTXSTT_W<1> {
        UCTXSTT_W::new(self)
    }
    #[doc = "Bit 2 - Transmit STOP"]
    #[inline(always)]
    pub fn uctxstp(&mut self) -> UCTXSTP_W<2> {
        UCTXSTP_W::new(self)
    }
    #[doc = "Bit 3 - Transmit NACK"]
    #[inline(always)]
    pub fn uctxnack(&mut self) -> UCTXNACK_W<3> {
        UCTXNACK_W::new(self)
    }
    #[doc = "Bit 4 - Transmit/Receive Select/Flag"]
    #[inline(always)]
    pub fn uctr(&mut self) -> UCTR_W<4> {
        UCTR_W::new(self)
    }
    #[doc = "Bits 6:7 - USCI 1 Clock Source Select 1"]
    #[inline(always)]
    pub fn ucssel(&mut self) -> UCSSEL_W<6> {
        UCSSEL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "USCI B0 Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucb0ctl1](index.html) module"]
pub struct UCB0CTL1_SPEC;
impl crate::RegisterSpec for UCB0CTL1_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [ucb0ctl1::R](R) reader structure"]
impl crate::Readable for UCB0CTL1_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ucb0ctl1::W](W) writer structure"]
impl crate::Writable for UCB0CTL1_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets UCB0CTL1 to value 0"]
impl crate::Resettable for UCB0CTL1_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}