Struct msp430fr2x5x_hal::clock::ClockConfig

pub struct ClockConfig<MCLK, SMCLK> { /* fields omitted */ }

Builder object that configures system clocks

Can only commit configurations to hardware if both MCLK and SMCLK settings have been configured. ACLK configurations are optional, with its default source being REFOCLK.

Implementations

impl ClockConfig<NoClockDefined, NoClockDefined>

pub fn new(cs: CS) -> Self

Converts CS into a fresh, unconfigured clock builder object

impl<MCLK, SMCLK> ClockConfig<MCLK, SMCLK>

pub fn aclk_refoclk(self) -> Self

Select REFOCLK for ACLK

pub fn aclk_vloclk(self) -> Self

Select VLOCLK for ACLK

pub fn mclk_refoclk(self, mclk_div: MclkDiv) -> ClockConfig<MclkDefined, SMCLK>

Select REFOCLK for MCLK and set the MCLK divider. Frequency is 10000 / mclk_div Hz.

pub fn mclk_vcoclk(self, mclk_div: MclkDiv) -> ClockConfig<MclkDefined, SMCLK>

Select VLOCLK for MCLK and set the MCLK divider. Frequency is 32768 / mclk_div Hz.

pub fn mclk_dcoclk(
    self,
    target_freq: DcoclkFreqSel,
    mclk_div: MclkDiv
) -> ClockConfig<MclkDefined, SMCLK>

Select DCOCLK for MCLK with FLL for stabilization. Frequency is target_freq / mclk_div Hz. This setting selects the default factory trim for DCO trimming and performs no extra calibration, so only a select few frequency targets can be selected.

pub fn smclk_on(self, div: SmclkDiv) -> ClockConfig<MCLK, SmclkDefined>

Enable SMCLK and set SMCLK divider, which divides the MCLK frequency

pub fn smclk_off(self) -> ClockConfig<MCLK, SmclkDisabled>

Disable SMCLK

impl ClockConfig<MclkDefined, SmclkDefined>

pub fn freeze(self, fram: &mut Fram) -> (Smclk, Aclk)

Apply clock configuration to hardware and return SMCLK and ACLK clock objects

impl ClockConfig<MclkDefined, SmclkDisabled>

pub fn freeze(self, fram: &mut Fram) -> Aclk

Apply clock configuration to hardware and return ACLK clock object, as SMCLK is disabled