Enum msp430f5529::dma::dmactl0::DMA0TSEL_A

#[repr(u8)]
pub enum DMA0TSEL_A {
    DMA0TSEL_0,
    DMA0TSEL_1,
    DMA0TSEL_2,
    DMA0TSEL_3,
    DMA0TSEL_4,
    DMA0TSEL_5,
    DMA0TSEL_6,
    DMA0TSEL_7,
    DMA0TSEL_8,
    DMA0TSEL_9,
    DMA0TSEL_10,
    DMA0TSEL_11,
    DMA0TSEL_12,
    DMA0TSEL_13,
    DMA0TSEL_14,
    DMA0TSEL_15,
    DMA0TSEL_16,
    DMA0TSEL_17,
    DMA0TSEL_18,
    DMA0TSEL_19,
    DMA0TSEL_20,
    DMA0TSEL_21,
    DMA0TSEL_22,
    DMA0TSEL_23,
    DMA0TSEL_24,
    DMA0TSEL_25,
    DMA0TSEL_26,
    DMA0TSEL_27,
    DMA0TSEL_28,
    DMA0TSEL_29,
    DMA0TSEL_30,
    DMA0TSEL_31,
}

DMA channel 0 transfer select bit 0

Value on reset: 0

Variants

DMA0TSEL_0

0: DMA channel 0 transfer select 0: DMA_REQ (sw)

DMA0TSEL_1

1: DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG)

DMA0TSEL_2

2: DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG)

DMA0TSEL_3

3: DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG)

DMA0TSEL_4

4: DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG)

DMA0TSEL_5

5: DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG)

DMA0TSEL_6

6: DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG)

DMA0TSEL_7

7: DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG)

DMA0TSEL_8

8: DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG)

DMA0TSEL_9

9: DMA channel 0 transfer select 9: Reserved

DMA0TSEL_10

10: DMA channel 0 transfer select 10: Reserved

DMA0TSEL_11

11: DMA channel 0 transfer select 11: Reserved

DMA0TSEL_12

12: DMA channel 0 transfer select 12: Reserved

DMA0TSEL_13

13: DMA channel 0 transfer select 13: Reserved

DMA0TSEL_14

14: DMA channel 0 transfer select 14: Reserved

DMA0TSEL_15

15: DMA channel 0 transfer select 15: Reserved

DMA0TSEL_16

16: DMA channel 0 transfer select 16: USCIA0 receive

DMA0TSEL_17

17: DMA channel 0 transfer select 17: USCIA0 transmit

DMA0TSEL_18

18: DMA channel 0 transfer select 18: USCIB0 receive

DMA0TSEL_19

19: DMA channel 0 transfer select 19: USCIB0 transmit

DMA0TSEL_20

20: DMA channel 0 transfer select 20: USCIA1 receive

DMA0TSEL_21

21: DMA channel 0 transfer select 21: USCIA1 transmit

DMA0TSEL_22

22: DMA channel 0 transfer select 22: USCIB1 receive

DMA0TSEL_23

23: DMA channel 0 transfer select 23: USCIB1 transmit

DMA0TSEL_24

24: DMA channel 0 transfer select 24: ADC12IFGx

DMA0TSEL_25

25: DMA channel 0 transfer select 25: Reserved

DMA0TSEL_26

26: DMA channel 0 transfer select 26: Reserved

DMA0TSEL_27

27: DMA channel 0 transfer select 27: USB FNRXD

DMA0TSEL_28

28: DMA channel 0 transfer select 28: USB ready

DMA0TSEL_29

29: DMA channel 0 transfer select 29: Multiplier ready

DMA0TSEL_30

30: DMA channel 0 transfer select 30: previous DMA channel DMA2IFG

DMA0TSEL_31

31: DMA channel 0 transfer select 31: ext. Trigger (DMAE0)

Trait Implementations

impl Clone for DMA0TSEL_A

fn clone(&self) -> DMA0TSEL_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DMA0TSEL_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<DMA0TSEL_A> for u8

fn from(variant: DMA0TSEL_A) -> Self

Performs the conversion.

impl PartialEq<DMA0TSEL_A> for DMA0TSEL_A

fn eq(&self, other: &DMA0TSEL_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for DMA0TSEL_A

impl StructuralPartialEq for DMA0TSEL_A