Struct moore_svlog_syntax::ast::SubroutinePortName

pub struct SubroutinePortName<'a> {
    pub name: Spanned<Name>,
    pub dims: Vec<TypeDim<'a>>,
    pub expr: Option<Expr<'a>>,
}

Fields

name: Spanned<Name>

dims: Vec<TypeDim<'a>>

expr: Option<Expr<'a>>

Trait Implementations

impl<'a> AcceptVisitor<'a> for SubroutinePortName<'a>

fn accept(&'a self, visitor: &mut dyn Visitor<'a>)

Walk a visitor over the contents of self.

impl<'a> Clone for SubroutinePortName<'a>

fn clone(&self) -> SubroutinePortName<'a>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<'a> Debug for SubroutinePortName<'a>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'a> Eq for SubroutinePortName<'a>

impl<'a> ForEachChild<'a> for SubroutinePortName<'a>

fn for_each_child(&'a self, each: &mut dyn FnMut(&'a dyn AnyNode<'a>))

Apply a function to each child node.

impl<'a> ForEachNode<'a> for SubroutinePortName<'a>

fn for_each_node(&'a self, each: &mut dyn FnMut(&'a dyn AnyNode<'a>))

Apply a function to this node.

impl<'a> PartialEq<SubroutinePortName<'a>> for SubroutinePortName<'a>

fn eq(&self, other: &SubroutinePortName<'a>) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &SubroutinePortName<'a>) -> bool

This method tests for !=.

impl<'a> StructuralEq for SubroutinePortName<'a>

impl<'a> StructuralPartialEq for SubroutinePortName<'a>

impl<'a> WalkVisitor<'a> for SubroutinePortName<'a>

fn walk(&'a self, visitor: &mut dyn Visitor<'a>)

Walk a visitor over self.

Calling this function is equivalent to calling:

• visitor.pre_visit_subroutine_port_name(self)
• self.accept(visitor)
• visitor.post_visit_subroutine_port_name(self);