Struct mkw41z::dcdc::reg0::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn dcdc_disable_auto_clk_switch(&self) -> DCDC_DISABLE_AUTO_CLK_SWITCHR[src]
Bit 1 - Disable automatic clock switch from internal oscillator to external clock.
pub fn dcdc_sel_clk(&self) -> DCDC_SEL_CLKR[src]
Bit 2 - Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set.
pub fn dcdc_pwd_osc_int(&self) -> DCDC_PWD_OSC_INTR[src]
Bit 3 - Power down internal oscillator. Only set this bit when 32M crystal oscillator is available.
pub fn dcdc_lp_df_cmp_enable(&self) -> DCDC_LP_DF_CMP_ENABLER[src]
Bit 9 - Enable low power differential comparators, to sense lower supply in pulsed mode
pub fn dcdc_vbat_div_ctrl(&self) -> DCDC_VBAT_DIV_CTRLR[src]
Bits 10:11 - Controls VBAT voltage divider
pub fn dcdc_lp_state_hys_l(&self) -> DCDC_LP_STATE_HYS_LR[src]
Bits 17:18 - Configure the hysteretic lower threshold value in low power mode
pub fn dcdc_lp_state_hys_h(&self) -> DCDC_LP_STATE_HYS_HR[src]
Bits 19:20 - Configure the hysteretic upper threshold value in low power mode
pub fn hyst_lp_comp_adj(&self) -> HYST_LP_COMP_ADJR[src]
Bit 21 - Adjust hysteretic value in low power comparator.
pub fn hyst_lp_cmp_disable(&self) -> HYST_LP_CMP_DISABLER[src]
Bit 22 - Disable hysteresis in low power comparator.
pub fn offset_rsns_lp_adj(&self) -> OFFSET_RSNS_LP_ADJR[src]
Bit 23 - Adjust hysteretic value in low power voltage sense.
pub fn offset_rsns_lp_disable(&self) -> OFFSET_RSNS_LP_DISABLER[src]
Bit 24 - Disable hysteresis in low power voltage sense.
pub fn dcdc_less_i(&self) -> DCDC_LESS_IR[src]
Bit 25 - Reduce DCDC current. It will save approximately 20 uA in RUN.
pub fn pwd_cmp_offset(&self) -> PWD_CMP_OFFSETR[src]
Bit 26 - Power down output range comparator
pub fn dcdc_xtalok_disable(&self) -> DCDC_XTALOK_DISABLER[src]
Bit 27 - Disable xtalok detection circuit.
pub fn pswitch_status(&self) -> PSWITCH_STATUSR[src]
Bit 28 - Status register to indicate PSWITCH status
pub fn vlps_config_dcdc_hp(&self) -> VLPS_CONFIG_DCDC_HPR[src]
Bit 29 - Selects behavior of DCDC in device VLPS low power mode
pub fn vlpr_vlpw_config_dcdc_hp(&self) -> VLPR_VLPW_CONFIG_DCDC_HPR[src]
Bit 30 - Selects behavior of DCDC in device VLPR and VLPW low power modes
pub fn dcdc_sts_dc_ok(&self) -> DCDC_STS_DC_OKR[src]
Bit 31 - Status register to indicate DCDC lock