Struct mkw41z::dma::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub cr: CR, pub es: ES, pub erq: ERQ, pub eei: EEI, pub ceei: CEEI, pub seei: SEEI, pub cerq: CERQ, pub serq: SERQ, pub cdne: CDNE, pub ssrt: SSRT, pub cerr: CERR, pub cint: CINT, pub int: INT, pub err: ERR, pub hrs: HRS, pub ears: EARS, pub dchpri3: DCHPRI, pub dchpri2: DCHPRI, pub dchpri1: DCHPRI, pub dchpri0: DCHPRI, pub tcd0_saddr: TCD_SADDR, pub tcd0_soff: TCD_SOFF, pub tcd0_attr: TCD_ATTR, pub tcd0_nbytes_mlno: TCD_NBYTES_MLNO, pub tcd0_slast: TCD_SLAST, pub tcd0_daddr: TCD_DADDR, pub tcd0_doff: TCD_DOFF, pub tcd0_citer_elinkno: TCD_CITER_ELINKNO, pub tcd0_dlastsga: TCD_DLASTSGA, pub tcd0_csr: TCD_CSR, pub tcd0_biter_elinkno: TCD_BITER_ELINKNO, pub tcd1_saddr: TCD_SADDR, pub tcd1_soff: TCD_SOFF, pub tcd1_attr: TCD_ATTR, pub tcd1_nbytes_mlno: TCD_NBYTES_MLNO, pub tcd1_slast: TCD_SLAST, pub tcd1_daddr: TCD_DADDR, pub tcd1_doff: TCD_DOFF, pub tcd1_citer_elinkno: TCD_CITER_ELINKNO, pub tcd1_dlastsga: TCD_DLASTSGA, pub tcd1_csr: TCD_CSR, pub tcd1_biter_elinkno: TCD_BITER_ELINKNO, pub tcd2_saddr: TCD_SADDR, pub tcd2_soff: TCD_SOFF, pub tcd2_attr: TCD_ATTR, pub tcd2_nbytes_mlno: TCD_NBYTES_MLNO, pub tcd2_slast: TCD_SLAST, pub tcd2_daddr: TCD_DADDR, pub tcd2_doff: TCD_DOFF, pub tcd2_citer_elinkno: TCD_CITER_ELINKNO, pub tcd2_dlastsga: TCD_DLASTSGA, pub tcd2_csr: TCD_CSR, pub tcd2_biter_elinkno: TCD_BITER_ELINKNO, pub tcd3_saddr: TCD_SADDR, pub tcd3_soff: TCD_SOFF, pub tcd3_attr: TCD_ATTR, pub tcd3_nbytes_mlno: TCD_NBYTES_MLNO, pub tcd3_slast: TCD_SLAST, pub tcd3_daddr: TCD_DADDR, pub tcd3_doff: TCD_DOFF, pub tcd3_citer_elinkno: TCD_CITER_ELINKNO, pub tcd3_dlastsga: TCD_DLASTSGA, pub tcd3_csr: TCD_CSR, pub tcd3_biter_elinkno: TCD_BITER_ELINKNO, // some fields omitted }
Register block
Fields
cr: CR
0x00 - Control Register
es: ES
0x04 - Error Status Register
erq: ERQ
0x0c - Enable Request Register
eei: EEI
0x14 - Enable Error Interrupt Register
ceei: CEEI
0x18 - Clear Enable Error Interrupt Register
seei: SEEI
0x19 - Set Enable Error Interrupt Register
cerq: CERQ
0x1a - Clear Enable Request Register
serq: SERQ
0x1b - Set Enable Request Register
cdne: CDNE
0x1c - Clear DONE Status Bit Register
ssrt: SSRT
0x1d - Set START Bit Register
cerr: CERR
0x1e - Clear Error Register
cint: CINT
0x1f - Clear Interrupt Request Register
int: INT
0x24 - Interrupt Request Register
err: ERR
0x2c - Error Register
hrs: HRS
0x34 - Hardware Request Status Register
ears: EARS
0x44 - Enable Asynchronous Request in Stop Register
dchpri3: DCHPRI
0x100 - Channel n Priority Register
dchpri2: DCHPRI
0x101 - Channel n Priority Register
dchpri1: DCHPRI
0x102 - Channel n Priority Register
dchpri0: DCHPRI
0x103 - Channel n Priority Register
tcd0_saddr: TCD_SADDR
0x1000 - TCD Source Address
tcd0_soff: TCD_SOFF
0x1004 - TCD Signed Source Address Offset
tcd0_attr: TCD_ATTR
0x1006 - TCD Transfer Attributes
tcd0_nbytes_mlno: TCD_NBYTES_MLNO
0x1008 - TCD Minor Byte Count (Minor Loop Mapping Disabled)
tcd0_slast: TCD_SLAST
0x100c - TCD Last Source Address Adjustment
tcd0_daddr: TCD_DADDR
0x1010 - TCD Destination Address
tcd0_doff: TCD_DOFF
0x1014 - TCD Signed Destination Address Offset
tcd0_citer_elinkno: TCD_CITER_ELINKNO
0x1016 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd0_dlastsga: TCD_DLASTSGA
0x1018 - TCD Last Destination Address Adjustment/Scatter Gather Address
tcd0_csr: TCD_CSR
0x101c - TCD Control and Status
tcd0_biter_elinkno: TCD_BITER_ELINKNO
0x101e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd1_saddr: TCD_SADDR
0x1020 - TCD Source Address
tcd1_soff: TCD_SOFF
0x1024 - TCD Signed Source Address Offset
tcd1_attr: TCD_ATTR
0x1026 - TCD Transfer Attributes
tcd1_nbytes_mlno: TCD_NBYTES_MLNO
0x1028 - TCD Minor Byte Count (Minor Loop Mapping Disabled)
tcd1_slast: TCD_SLAST
0x102c - TCD Last Source Address Adjustment
tcd1_daddr: TCD_DADDR
0x1030 - TCD Destination Address
tcd1_doff: TCD_DOFF
0x1034 - TCD Signed Destination Address Offset
tcd1_citer_elinkno: TCD_CITER_ELINKNO
0x1036 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd1_dlastsga: TCD_DLASTSGA
0x1038 - TCD Last Destination Address Adjustment/Scatter Gather Address
tcd1_csr: TCD_CSR
0x103c - TCD Control and Status
tcd1_biter_elinkno: TCD_BITER_ELINKNO
0x103e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd2_saddr: TCD_SADDR
0x1040 - TCD Source Address
tcd2_soff: TCD_SOFF
0x1044 - TCD Signed Source Address Offset
tcd2_attr: TCD_ATTR
0x1046 - TCD Transfer Attributes
tcd2_nbytes_mlno: TCD_NBYTES_MLNO
0x1048 - TCD Minor Byte Count (Minor Loop Mapping Disabled)
tcd2_slast: TCD_SLAST
0x104c - TCD Last Source Address Adjustment
tcd2_daddr: TCD_DADDR
0x1050 - TCD Destination Address
tcd2_doff: TCD_DOFF
0x1054 - TCD Signed Destination Address Offset
tcd2_citer_elinkno: TCD_CITER_ELINKNO
0x1056 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd2_dlastsga: TCD_DLASTSGA
0x1058 - TCD Last Destination Address Adjustment/Scatter Gather Address
tcd2_csr: TCD_CSR
0x105c - TCD Control and Status
tcd2_biter_elinkno: TCD_BITER_ELINKNO
0x105e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd3_saddr: TCD_SADDR
0x1060 - TCD Source Address
tcd3_soff: TCD_SOFF
0x1064 - TCD Signed Source Address Offset
tcd3_attr: TCD_ATTR
0x1066 - TCD Transfer Attributes
tcd3_nbytes_mlno: TCD_NBYTES_MLNO
0x1068 - TCD Minor Byte Count (Minor Loop Mapping Disabled)
tcd3_slast: TCD_SLAST
0x106c - TCD Last Source Address Adjustment
tcd3_daddr: TCD_DADDR
0x1070 - TCD Destination Address
tcd3_doff: TCD_DOFF
0x1074 - TCD Signed Destination Address Offset
tcd3_citer_elinkno: TCD_CITER_ELINKNO
0x1076 - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
tcd3_dlastsga: TCD_DLASTSGA
0x1078 - TCD Last Destination Address Adjustment/Scatter Gather Address
tcd3_csr: TCD_CSR
0x107c - TCD Control and Status
tcd3_biter_elinkno: TCD_BITER_ELINKNO
0x107e - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)