<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<vendor>Freescale Semiconductor, Inc.</vendor>
<vendorID>Freescale</vendorID>
<series>Kinetis_L</series>
<name>MKL26Z4</name>
<version>1.6</version>
<description>MKL26Z4 Freescale Microcontroller</description>
<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
<cpu>
<name>CM0PLUS</name>
<revision>r0p0</revision>
<endian>little</endian>
<fpuPresent>false</fpuPresent>
<mpuPresent>false</mpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>FTFA_FlashConfig</name>
<description>Flash configuration field</description>
<prependToName>NV_</prependToName>
<baseAddress>0x400</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>BACKKEY3</name>
<description>Backdoor Comparison Key 3.</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY2</name>
<description>Backdoor Comparison Key 2.</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY1</name>
<description>Backdoor Comparison Key 1.</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY0</name>
<description>Backdoor Comparison Key 0.</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY7</name>
<description>Backdoor Comparison Key 7.</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY6</name>
<description>Backdoor Comparison Key 6.</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY5</name>
<description>Backdoor Comparison Key 5.</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY4</name>
<description>Backdoor Comparison Key 4.</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT3</name>
<description>Non-volatile P-Flash Protection 1 - Low Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT2</name>
<description>Non-volatile P-Flash Protection 1 - High Register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT1</name>
<description>Non-volatile P-Flash Protection 0 - Low Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT0</name>
<description>Non-volatile P-Flash Protection 0 - High Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Non-volatile Flash Security Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Non-volatile Flash Option Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LPBOOT0</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NMI_DIS</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>NMI interrupts are always blocked</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>NMI_b pin/interrupts reset default to enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PIN_CFG</name>
<description>no description available</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>RESET pin is disabled following a POR and cannot be enabled as reset function</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>RESET_b pin is dedicated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPBOOT1</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST_INIT</name>
<description>no description available</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Slower initialization</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fast Initialization</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA</name>
<description>DMA Controller</description>
<prependToName>DMA_</prependToName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0x100</offset>
<size>0x40</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA0</name>
<value>0</value>
</interrupt>
<interrupt>
<name>DMA1</name>
<value>1</value>
</interrupt>
<interrupt>
<name>DMA2</name>
<value>2</value>
</interrupt>
<interrupt>
<name>DMA3</name>
<value>3</value>
</interrupt>
<registers>
<register>
<name>SAR0</name>
<description>Source Address Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>Each SAR contains the byte address used by the DMA controller to read data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR0</name>
<description>Destination Address Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>Each DAR contains the byte address used by the DMA controller to write data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR0</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>This field contains the number of bytes yet to be transferred for a given block</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR0</name>
<description>DMA_DSR0 register.</description>
<addressOffset>0x10B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR0</name>
<description>DMA Control Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR1</name>
<description>Source Address Register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>Each SAR contains the byte address used by the DMA controller to read data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR1</name>
<description>Destination Address Register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>Each DAR contains the byte address used by the DMA controller to write data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR1</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>This field contains the number of bytes yet to be transferred for a given block</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR1</name>
<description>DMA_DSR1 register.</description>
<addressOffset>0x11B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR1</name>
<description>DMA Control Register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR2</name>
<description>Source Address Register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>Each SAR contains the byte address used by the DMA controller to read data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR2</name>
<description>Destination Address Register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>Each DAR contains the byte address used by the DMA controller to write data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR2</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>This field contains the number of bytes yet to be transferred for a given block</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR2</name>
<description>DMA_DSR2 register.</description>
<addressOffset>0x12B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR2</name>
<description>DMA Control Register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SAR3</name>
<description>Source Address Register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAR</name>
<description>Each SAR contains the byte address used by the DMA controller to read data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAR3</name>
<description>Destination Address Register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DAR</name>
<description>Each DAR contains the byte address used by the DMA controller to write data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSR_BCR3</name>
<description>DMA Status Register / Byte Count Register</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BCR</name>
<description>This field contains the number of bytes yet to be transferred for a given block</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Transactions Done</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA transfer is not yet complete. Writing a 0 has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is inactive. Cleared when the DMA has finished the last transaction.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BSY is set the first time the channel is enabled after a transfer is initiated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQ</name>
<description>Request</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request is pending or the channel is currently active. Cleared when the channel is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel has a transfer remaining and the channel is not selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BED</name>
<description>Bus Error on Destination</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the write portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BES</name>
<description>Bus Error on Source</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus error occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA channel terminated with a bus error during the read portion of a transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CE</name>
<description>Configuration Error</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No configuration error exists.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A configuration error has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DSR3</name>
<description>DMA_DSR3 register.</description>
<addressOffset>0x13B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>DCR3</name>
<description>DMA Control Register</description>
<addressOffset>0x13C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCH2</name>
<description>Link Channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCH1</name>
<description>Link Channel 1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DMA Channel 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DMA Channel 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DMA Channel 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DMA Channel 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINKCC</name>
<description>Link Channel Control</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No channel-to-channel linking</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Perform a link to channel LCH1 after each cycle-steal transfer</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Perform a link to channel LCH1 after the BCR decrements to 0.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>D_REQ</name>
<description>Disable Request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ERQ bit is not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ERQ bit is cleared when the BCR is exhausted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Buffer disabled</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Circular buffer size is 16 bytes.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Circular buffer size is 32 bytes.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Circular buffer size is 64 bytes.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Circular buffer size is 128 bytes.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Circular buffer size is 256 bytes.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Circular buffer size is 512 bytes.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Circular buffer size is 1 KB.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Circular buffer size is 2 KB.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Circular buffer size is 4 KB.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Circular buffer size is 8 KB.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Circular buffer size is 16 KB.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Circular buffer size is 32 KB.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Circular buffer size is 64 KB.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Circular buffer size is 128 KB.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Circular buffer size is 256 KB.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Destination Size</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DINC</name>
<description>Destination Increment</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to the DAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAR increments by 1, 2, 4 depending upon the size of the transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIZE</name>
<description>Source Size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINC</name>
<description>Source Increment</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No change to SAR after a successful transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SAR increments by 1, 2, 4 as determined by the transfer size.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EADREQ</name>
<description>Enable asynchronous DMA requests</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AA</name>
<description>Auto-align</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto-align disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CS</name>
<description>Cycle Steal</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA continuously makes read/write transfers until the BCR decrements to 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Forces a single read/write transfer per request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ</name>
<description>Enable Peripheral Request</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripheral request is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EINT</name>
<description>Enable Interrupt on Completion of Transfer</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt is generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt signal is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTFA</name>
<description>Flash Memory Interface</description>
<prependToName>FTFA_</prependToName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTFA</name>
<value>5</value>
</interrupt>
<registers>
<register>
<name>FSTAT</name>
<description>Flash Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MGSTAT0</name>
<description>Memory Controller Command Completion Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FPVIOL</name>
<description>Flash Protection Violation Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No protection violation detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Protection violation detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCERR</name>
<description>Flash Access Error Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No access error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLERR</name>
<description>Flash Read Collision Error Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No collision error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Collision error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIF</name>
<description>Command Complete Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash command in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash command has completed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCNFG</name>
<description>Flash Configuration Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ERSSUSP</name>
<description>Erase Suspend</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No suspend requested</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Suspend the current Erase Flash Sector command execution.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERSAREQ</name>
<description>Erase All Request</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request or request complete</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLLIE</name>
<description>Read Collision Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read collision error interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIE</name>
<description>Command Complete Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Command complete interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Flash Security Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCU security status is secure.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCU security status is secure.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Freescale factory access granted</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Freescale factory access denied</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>Mass Erase Enable Bits</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Mass erase is enabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mass erase is enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Backdoor key access disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Flash Option Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>OPT</name>
<description>Nonvolatile Option</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
<name>FCCOB%s</name>
<description>Flash Common Command Object Registers</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CCOBn</name>
<description>The FCCOB register provides a command code and relevant parameters to the memory controller</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0</dimIndex>
<name>FPROT%s</name>
<description>Program Flash Protection Registers</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PROT</name>
<description>Program Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Program flash region is protected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Program flash region is not protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX0</name>
<description>DMA channel multiplexor</description>
<prependToName>DMAMUX0_</prependToName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>CHCFG%s</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable_Signal</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>UART0_Rx_Signal</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>UART0_Tx_Signal</description>
<value>#11</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>UART1_Rx_Signal</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>UART1_Tx_Signal</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>UART2_Rx_Signal</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>UART2_Tx_Signal</description>
<value>#111</value>
</enumeratedValue>
<enumeratedValue>
<name>14</name>
<description>I2S0_Rx_Signal</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>15</name>
<description>I2S0_Tx_Signal</description>
<value>#1111</value>
</enumeratedValue>
<enumeratedValue>
<name>16</name>
<description>SPI0_Rx_Signal</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>17</name>
<description>SPI0_Tx_Signal</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>18</name>
<description>SPI1_Rx_Signal</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>19</name>
<description>SPI1_Tx_Signal</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>22</name>
<description>I2C0_Signal</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>23</name>
<description>I2C1_Signal</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>24</name>
<description>TPM0_Channel0_Signal</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>25</name>
<description>TPM0_Channel1_Signal</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>26</name>
<description>TPM0_Channel2_Signal</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>27</name>
<description>TPM0_Channel3_Signal</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>28</name>
<description>TPM0_Channel4_Signal</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>29</name>
<description>TPM0_Channel5_Signal</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>32</name>
<description>TPM1_Channel0_Signal</description>
<value>#100000</value>
</enumeratedValue>
<enumeratedValue>
<name>33</name>
<description>TPM1_Channel1_Signal</description>
<value>#100001</value>
</enumeratedValue>
<enumeratedValue>
<name>34</name>
<description>TPM2_Channel0_Signal</description>
<value>#100010</value>
</enumeratedValue>
<enumeratedValue>
<name>35</name>
<description>TPM2_Channel1_Signal</description>
<value>#100011</value>
</enumeratedValue>
<enumeratedValue>
<name>40</name>
<description>ADC0_Signal</description>
<value>#101000</value>
</enumeratedValue>
<enumeratedValue>
<name>42</name>
<description>CMP0_Signal</description>
<value>#101010</value>
</enumeratedValue>
<enumeratedValue>
<name>45</name>
<description>DAC0_Signal</description>
<value>#101101</value>
</enumeratedValue>
<enumeratedValue>
<name>49</name>
<description>PortA_Signal</description>
<value>#110001</value>
</enumeratedValue>
<enumeratedValue>
<name>51</name>
<description>PortC_Signal</description>
<value>#110011</value>
</enumeratedValue>
<enumeratedValue>
<name>52</name>
<description>PortD_Signal</description>
<value>#110100</value>
</enumeratedValue>
<enumeratedValue>
<name>54</name>
<description>TPM0_Overflow_Signal</description>
<value>#110110</value>
</enumeratedValue>
<enumeratedValue>
<name>55</name>
<description>TPM1_Overflow_Signal</description>
<value>#110111</value>
</enumeratedValue>
<enumeratedValue>
<name>56</name>
<description>TPM2_Overflow_Signal</description>
<value>#111000</value>
</enumeratedValue>
<enumeratedValue>
<name>60</name>
<description>AlwaysOn60_Signal</description>
<value>#111100</value>
</enumeratedValue>
<enumeratedValue>
<name>61</name>
<description>AlwaysOn61_Signal</description>
<value>#111101</value>
</enumeratedValue>
<enumeratedValue>
<name>62</name>
<description>AlwaysOn62_Signal</description>
<value>#111110</value>
</enumeratedValue>
<enumeratedValue>
<name>63</name>
<description>AlwaysOn63_Signal</description>
<value>#111111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2S0</name>
<description>Inter-IC Sound / Synchronous Audio Interface</description>
<prependToName>I2S0_</prependToName>
<baseAddress>0x4002F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x108</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2S0</name>
<value>23</value>
</interrupt>
<registers>
<register>
<name>TCSR</name>
<description>SAI Transmit Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FWDE</name>
<description>FIFO Warning DMA Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the DMA request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the DMA request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FWIE</name>
<description>FIFO Warning Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>FIFO Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEIE</name>
<description>Sync Error Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WSIE</name>
<description>Word Start Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FWF</name>
<description>FIFO Warning Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No enabled transmit FIFO is empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled transmit FIFO is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEF</name>
<description>FIFO Error Flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit underrun not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit underrun detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEF</name>
<description>Sync Error Flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sync error not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync error detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WSF</name>
<description>Word Start Flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Start of word not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start of word detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SR</name>
<description>Software Reset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FR</name>
<description>FIFO Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCE</name>
<description>Bit Clock Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit bit clock is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit bit clock is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGE</name>
<description>Debug Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter is disabled in Debug mode, after completing the current frame.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter is enabled in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPE</name>
<description>Stop Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter enabled in Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCR2</name>
<description>SAI Transmit Configuration 2 Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Bit Clock Divide</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BCD</name>
<description>Bit Clock Direction</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bit clock is generated externally in Slave mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit clock is generated internally in Master mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCP</name>
<description>Bit Clock Polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSEL</name>
<description>MCLK Select</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Master Clock (MCLK) 1 option selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Master Clock (MCLK) 2 option selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Master Clock (MCLK) 3 option selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCI</name>
<description>Bit Clock Input</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal logic is clocked as if bit clock was externally generated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCS</name>
<description>Bit Clock Swap</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Use the normal bit clock source.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Swap the bit clock source.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNC</name>
<description>Synchronous Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Asynchronous mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Synchronous with receiver.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Synchronous with another SAI transmitter.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Synchronous with another SAI receiver.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCR3</name>
<description>SAI Transmit Configuration 3 Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDFL</name>
<description>Word Flag Configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCE</name>
<description>Transmit Channel Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data channel N is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data channel N is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCR4</name>
<description>SAI Transmit Configuration 4 Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FSD</name>
<description>Frame Sync Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame sync is generated externally in Slave mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync is generated internally in Master mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSP</name>
<description>Frame Sync Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame sync is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSE</name>
<description>Frame Sync Early</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame sync asserts with the first bit of the frame.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync asserts one bit before the first bit of the frame.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MF</name>
<description>MSB First</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB is transmitted first.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB is transmitted first.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYWD</name>
<description>Sync Width</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRSZ</name>
<description>Frame size</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCR5</name>
<description>SAI Transmit Configuration 5 Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FBT</name>
<description>First Bit Shifted</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>W0W</name>
<description>Word 0 Width</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WNW</name>
<description>Word N Width</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<description>SAI Transmit Data Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TDR</name>
<description>Transmit Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TMR</name>
<description>SAI Transmit Mask Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TWM</name>
<description>Transmit Word Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Word N is enabled.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Word N is masked. The transmit data pins are tri-stated when masked.</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCSR</name>
<description>SAI Receive Control Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FWDE</name>
<description>FIFO Warning DMA Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the DMA request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the DMA request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FWIE</name>
<description>FIFO Warning Interrupt Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>FIFO Error Interrupt Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEIE</name>
<description>Sync Error Interrupt Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WSIE</name>
<description>Word Start Interrupt Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FWF</name>
<description>FIFO Warning Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No enabled receive FIFO is full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled receive FIFO is full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEF</name>
<description>FIFO Error Flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive overflow not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive overflow detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEF</name>
<description>Sync Error Flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sync error not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync error detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WSF</name>
<description>Word Start Flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Start of word not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start of word detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SR</name>
<description>Software Reset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FR</name>
<description>FIFO Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCE</name>
<description>Bit Clock Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive bit clock is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive bit clock is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGE</name>
<description>Debug Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver is disabled in Debug mode, after completing the current frame.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver is enabled in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPE</name>
<description>Stop Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver enabled in Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCR2</name>
<description>SAI Receive Configuration 2 Register</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>Bit Clock Divide</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BCD</name>
<description>Bit Clock Direction</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bit clock is generated externally in Slave mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit clock is generated internally in Master mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCP</name>
<description>Bit Clock Polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSEL</name>
<description>MCLK Select</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus Clock selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Master Clock (MCLK) 1 option selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Master Clock (MCLK) 2 option selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Master Clock (MCLK) 3 option selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCI</name>
<description>Bit Clock Input</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal logic is clocked as if bit clock was externally generated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCS</name>
<description>Bit Clock Swap</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Use the normal bit clock source.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Swap the bit clock source.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNC</name>
<description>Synchronous Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Asynchronous mode.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Synchronous with transmitter.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Synchronous with another SAI receiver.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Synchronous with another SAI transmitter.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCR3</name>
<description>SAI Receive Configuration 3 Register</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDFL</name>
<description>Word Flag Configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RCE</name>
<description>Receive Channel Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data channel N is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data channel N is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCR4</name>
<description>SAI Receive Configuration 4 Register</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FSD</name>
<description>Frame Sync Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame Sync is generated externally in Slave mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame Sync is generated internally in Master mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSP</name>
<description>Frame Sync Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame sync is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSE</name>
<description>Frame Sync Early</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frame sync asserts with the first bit of the frame.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame sync asserts one bit before the first bit of the frame.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MF</name>
<description>MSB First</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB is received first.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB is received first.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYWD</name>
<description>Sync Width</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRSZ</name>
<description>Frame Size</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCR5</name>
<description>SAI Receive Configuration 5 Register</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FBT</name>
<description>First Bit Shifted</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>W0W</name>
<description>Word 0 Width</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WNW</name>
<description>Word N Width</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<description>SAI Receive Data Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDR</name>
<description>Receive Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RMR</name>
<description>SAI Receive Mask Register</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RWM</name>
<description>Receive Word Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Word N is enabled.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Word N is masked.</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>SAI MCLK Control Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MICS</name>
<description>MCLK Input Clock Select</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCLK divider input clock 0 selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCLK divider input clock 1 selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>MCLK divider input clock 2 selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCLK divider input clock 3 selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MOE</name>
<description>MCLK Output Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCLK signal pin is configured as an input that bypasses the MCLK divider.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DUF</name>
<description>Divider Update Flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCLK divider ratio is not being updated currently.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MDR</name>
<description>SAI MCLK Divide Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVIDE</name>
<description>MCLK Divide</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRACT</name>
<description>MCLK Fraction</description>
<bitOffset>12</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PIT</name>
<description>Periodic Interrupt Timer</description>
<prependToName>PIT_</prependToName>
<baseAddress>0x40037000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x120</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIT</name>
<value>22</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>PIT Module Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timers continue to run in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timers are stopped in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable - (PIT section)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock for standard PIT timers is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock for standard PIT timers is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LTMR64H</name>
<description>PIT Upper Lifetime Timer Register</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LTH</name>
<description>Life Timer value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LTMR64L</name>
<description>PIT Lower Lifetime Timer Register</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LTL</name>
<description>Life Timer value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>LDVAL%s</name>
<description>Timer Load Value Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSV</name>
<description>Timer Start Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CVAL%s</name>
<description>Current Timer Value Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TVL</name>
<description>Current Timer Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TCTRL%s</name>
<description>Timer Control Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer n is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer n is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt requests from Timer n are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt will be requested whenever TIF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHN</name>
<description>Chain Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not chained.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>TFLG%s</name>
<description>Timer Flag Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout has not yet occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TPM0</name>
<description>Timer/PWM Module</description>
<groupName>TPM</groupName>
<prependToName>TPM0_</prependToName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x88</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TPM0</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status and Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMOD</name>
<description>Clock Mode Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>TPM counter increments on every TPM counter clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter operates in up counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter operates in up-down counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling or DMA request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>6</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status and Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>6</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture and Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOZEEN</name>
<description>Doze Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal TPM counter continues in Doze mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMODE</name>
<description>Debug Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>TPM counter continues in debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEEN</name>
<description>Global time base enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All channels use the internally generated TPM counter as their timebase</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All channels use an externally generated global timebase as their timebase</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOT</name>
<description>Counter Start on Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter starts to increment immediately, once it is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOO</name>
<description>Counter Stop On Overflow</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter continues incrementing or decrementing after overflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter stops incrementing or decrementing after overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CROT</name>
<description>Counter Reload On Trigger</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL</name>
<description>Trigger Select</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TPM1</name>
<description>Timer/PWM Module</description>
<groupName>TPM</groupName>
<prependToName>TPM1_</prependToName>
<baseAddress>0x40039000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x88</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TPM1</name>
<value>18</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status and Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMOD</name>
<description>Clock Mode Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>TPM counter increments on every TPM counter clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter operates in up counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter operates in up-down counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling or DMA request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status and Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture and Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOZEEN</name>
<description>Doze Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal TPM counter continues in Doze mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMODE</name>
<description>Debug Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>TPM counter continues in debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEEN</name>
<description>Global time base enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All channels use the internally generated TPM counter as their timebase</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All channels use an externally generated global timebase as their timebase</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOT</name>
<description>Counter Start on Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter starts to increment immediately, once it is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOO</name>
<description>Counter Stop On Overflow</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter continues incrementing or decrementing after overflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter stops incrementing or decrementing after overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CROT</name>
<description>Counter Reload On Trigger</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL</name>
<description>Trigger Select</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TPM2</name>
<description>Timer/PWM Module</description>
<groupName>TPM</groupName>
<prependToName>TPM2_</prependToName>
<baseAddress>0x4003A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x88</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TPM2</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status and Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMOD</name>
<description>Clock Mode Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>TPM counter increments on every TPM counter clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter operates in up counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter operates in up-down counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling or DMA request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status and Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture and Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOZEEN</name>
<description>Doze Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal TPM counter continues in Doze mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMODE</name>
<description>Debug Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>TPM counter continues in debug mode.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEEN</name>
<description>Global time base enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All channels use the internally generated TPM counter as their timebase</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All channels use an externally generated global timebase as their timebase</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOT</name>
<description>Counter Start on Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter starts to increment immediately, once it is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSOO</name>
<description>Counter Stop On Overflow</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM counter continues incrementing or decrementing after overflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM counter stops incrementing or decrementing after overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CROT</name>
<description>Counter Reload On Trigger</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter is not reloaded due to a rising edge on the selected input trigger</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter is reloaded when a rising edge is detected on the selected input trigger</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL</name>
<description>Trigger Select</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC0</name>
<description>Analog-to-Digital Converter</description>
<prependToName>ADC0_</prependToName>
<baseAddress>0x4003B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x70</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC0</name>
<value>15</value>
</interrupt>
<registers>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>SC1%s</name>
<description>ADC Status and Control Registers 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADCH</name>
<description>Input channel select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Module is disabled.</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIFF</name>
<description>Differential Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single-ended conversions and input channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Differential conversions and input channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AIEN</name>
<description>Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion complete interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion complete interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COCO</name>
<description>Conversion Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion is not completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion is completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG1</name>
<description>ADC Configuration Register 1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADICLK</name>
<description>Input Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate clock 2 (ALTCLK2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Alternate clock (ALTCLK)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Asynchronous clock (ADACK)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Conversion mode selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLSMP</name>
<description>Sample Time Configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Short sample time.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Long sample time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADIV</name>
<description>Clock Divide Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The divide ratio is 1 and the clock rate is input clock.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLPC</name>
<description>Low-Power Configuration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal power configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<description>ADC Configuration Register 2</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADLSTS</name>
<description>Long Sample Time Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADHSC</name>
<description>High-Speed Configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal conversion sequence selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACKEN</name>
<description>Asynchronous Clock Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUXSEL</name>
<description>ADC Mux Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADxxa channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADxxb channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>R%s</name>
<description>ADC Data Result Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>D</name>
<description>Data result</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1,2</dimIndex>
<name>CV%s</name>
<description>Compare Value Registers</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CV</name>
<description>Compare Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC2</name>
<description>Status and Control Register 2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REFSEL</name>
<description>Voltage Reference Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACREN</name>
<description>Compare Function Range Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range function disabled. Only CV1 is compared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFGT</name>
<description>Compare Function Greater Than Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFE</name>
<description>Compare Function Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADTRG</name>
<description>Conversion Trigger Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACT</name>
<description>Conversion Active</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion not in progress.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion in progress.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC3</name>
<description>Status and Control Register 3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AVGS</name>
<description>Hardware Average Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>4 samples averaged.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8 samples averaged.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16 samples averaged.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>32 samples averaged.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVGE</name>
<description>Hardware Average Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware average function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware average function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCO</name>
<description>Continuous Conversion Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALF</name>
<description>Calibration Failed Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Calibration completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAL</name>
<description>Calibration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OFS</name>
<description>ADC Offset Correction Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFS</name>
<description>Offset Error Correction Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PG</name>
<description>ADC Plus-Side Gain Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PG</name>
<description>Plus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MG</name>
<description>ADC Minus-Side Gain Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MG</name>
<description>Minus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPD</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPS</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP4</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP3</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP2</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP1</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP0</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMD</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMS</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM4</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM3</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM2</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM1</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM0</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Secure Real Time Clock</description>
<prependToName>RTC_</prependToName>
<baseAddress>0x4003D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC</name>
<value>20</value>
</interrupt>
<interrupt>
<name>RTC_Seconds</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>TSR</name>
<description>RTC Time Seconds Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSR</name>
<description>Time Seconds Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TPR</name>
<description>RTC Time Prescaler Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TPR</name>
<description>Time Prescaler Register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TAR</name>
<description>RTC Time Alarm Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TAR</name>
<description>Time Alarm Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>RTC Time Compensation Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCR</name>
<description>Time Compensation Register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>10000000</name>
<description>Time Prescaler Register overflows every 32896 clock cycles.</description>
<value>#10000000</value>
</enumeratedValue>
<enumeratedValue>
<name>11111111</name>
<description>Time Prescaler Register overflows every 32769 clock cycles.</description>
<value>#11111111</value>
</enumeratedValue>
<enumeratedValue>
<name>0</name>
<description>Time Prescaler Register overflows every 32768 clock cycles.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time Prescaler Register overflows every 32767 clock cycles.</description>
<value>#1</value>
</enumeratedValue>
<enumeratedValue>
<name>1111111</name>
<description>Time Prescaler Register overflows every 32641 clock cycles.</description>
<value>#1111111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIR</name>
<description>Compensation Interval Register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCV</name>
<description>Time Compensation Value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CIC</name>
<description>Compensation Interval Counter</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CR</name>
<description>RTC Control Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SWR</name>
<description>Software Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPE</name>
<description>Wakeup Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wakeup pin is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUP</name>
<description>Supervisor Access</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Non-supervisor mode write accesses are not supported and generate a bus error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Non-supervisor mode write accesses are supported.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UM</name>
<description>Update Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Registers cannot be written when locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Registers can be written when locked under limited conditions.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPS</name>
<description>Wakeup Pin Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCE</name>
<description>Oscillator Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>32.768 kHz oscillator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKO</name>
<description>Clock Output</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The 32 kHz clock is output to other peripherals.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The 32 kHz clock is not output to other peripherals.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC16P</name>
<description>Oscillator 16pF Load Configure</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the load.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable the additional load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC8P</name>
<description>Oscillator 8pF Load Configure</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the load.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable the additional load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC4P</name>
<description>Oscillator 4pF Load Configure</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the load.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable the additional load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC2P</name>
<description>Oscillator 2pF Load Configure</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the load.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable the additional load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>RTC Status Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Time Invalid Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time is valid.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time is invalid and time counter is read as zero.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Time Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time overflow has not occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time overflow has occurred and time counter is read as zero.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAF</name>
<description>Time Alarm Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time alarm has not occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time alarm has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCE</name>
<description>Time Counter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time counter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time counter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LR</name>
<description>RTC Lock Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCL</name>
<description>Time Compensation Lock</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time Compensation Register is locked and writes are ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time Compensation Register is not locked and writes complete as normal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRL</name>
<description>Control Register Lock</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Control Register is locked and writes are ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Control Register is not locked and writes complete as normal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRL</name>
<description>Status Register Lock</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Status Register is locked and writes are ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Status Register is not locked and writes complete as normal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRL</name>
<description>Lock Register Lock</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Lock Register is locked and writes are ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Lock Register is not locked and writes complete as normal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>RTC Interrupt Enable Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIIE</name>
<description>Time Invalid Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time invalid flag does not generate an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time invalid flag does generate an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Time Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time overflow flag does not generate an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time overflow flag does generate an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAIE</name>
<description>Time Alarm Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time alarm flag does not generate an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time alarm flag does generate an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSIE</name>
<description>Time Seconds Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Seconds interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Seconds interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPON</name>
<description>Wakeup Pin On</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If the wakeup pin is enabled, then the wakeup pin will assert.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC0</name>
<description>12-Bit Digital-to-Analog Converter</description>
<prependToName>DAC0_</prependToName>
<baseAddress>0x4003F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DAC0</name>
<value>25</value>
</interrupt>
<registers>
<register>
<dim>2</dim>
<dimIncrement>0x2</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>DAT%sL</name>
<description>DAC Data Low Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x2</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>DAT%sH</name>
<description>DAC Data High Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA1</name>
<description>When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>DAC Status Register</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFRPBF</name>
<description>DAC Buffer Read Pointer Bottom Position Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer is not equal to C2[DACBFUP].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer is equal to C2[DACBFUP].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFRPTF</name>
<description>DAC Buffer Read Pointer Top Position Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer is not zero.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer is zero.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C0</name>
<description>DAC Control Register</description>
<addressOffset>0x21</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBBIEN</name>
<description>DAC Buffer Read Pointer Bottom Flag Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer bottom flag interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer bottom flag interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBTIEN</name>
<description>DAC Buffer Read Pointer Top Flag Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer top flag interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer top flag interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPEN</name>
<description>DAC Low Power Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>High-Power mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-Power mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACSWTRG</name>
<description>DAC Software Trigger</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC soft trigger is not valid.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC soft trigger is valid.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACTRGSEL</name>
<description>DAC Trigger Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC hardware trigger is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC software trigger is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACRFS</name>
<description>DAC Reference Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC selects DACREF_1 as the reference voltage.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC selects DACREF_2 as the reference voltage.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC system is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC system is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>DAC Control Register 1</description>
<addressOffset>0x22</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFEN</name>
<description>DAC Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer read pointer is disabled. The converted data is always the first word of the buffer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFMD</name>
<description>DAC Buffer Work Mode Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One-Time Scan mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>DAC Control Register 2</description>
<addressOffset>0x23</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFUP</name>
<description>DAC Buffer Upper Limit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DACBFRP</name>
<description>DAC Buffer Read Pointer</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTMR0</name>
<description>Low Power Timer</description>
<prependToName>LPTMR0_</prependToName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTMR0</name>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CSR</name>
<description>Low Power Timer Control Status Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPTMR is disabled and internal logic is reset.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPTMR is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMS</name>
<description>Timer Mode Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time Counter mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFC</name>
<description>Timer Free-Running Counter</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNR is reset whenever TCF is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNR is reset on overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPP</name>
<description>Timer Pin Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPS</name>
<description>Timer Pin Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pulse counter input 0 is selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pulse counter input 1 is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pulse counter input 2 is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Pulse counter input 3 is selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer interrupt disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer interrupt enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The value of CNR is not equal to CMR and increments.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The value of CNR is equal to CMR and increments.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<description>Low Power Timer Prescale Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCS</name>
<description>Prescaler Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Prescaler/glitch filter clock 0 selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Prescaler/glitch filter clock 1 selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Prescaler/glitch filter clock 2 selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Prescaler/glitch filter clock 3 selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PBYP</name>
<description>Prescaler Bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prescaler/glitch filter is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prescaler/glitch filter is bypassed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALE</name>
<description>Prescale Value</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CMR</name>
<description>Low Power Timer Compare Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMPARE</name>
<description>Compare Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNR</name>
<description>Low Power Timer Counter Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TSI0</name>
<description>Touch sense input</description>
<prependToName>TSI0_</prependToName>
<baseAddress>0x40045000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TSI0</name>
<value>26</value>
</interrupt>
<registers>
<register>
<name>GENCS</name>
<description>TSI General Control and Status Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CURSW</name>
<description>CURSW</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The current source pair are not swapped.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The current source pair are swapped.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOSF</name>
<description>End of Scan Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Scan not complete.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Scan complete.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCNIP</name>
<description>Scan In Progress Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No scan in progress.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Scan in progress.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STM</name>
<description>Scan Trigger Mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger scan.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger scan.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STPE</name>
<description>TSI STOP Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TSI is disabled when MCU goes into low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Allows TSI to continue running in all low power modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSIIEN</name>
<description>Touch Sensing Input Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TSI interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TSI interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSIEN</name>
<description>Touch Sensing Input Module Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TSI module disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TSI module enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSCN</name>
<description>NSCN</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>Once per electrode</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>Twice per electrode</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>3 times per electrode</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>4 times per electrode</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>5 times per electrode</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>6 times per electrode</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>7 times per electrode</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>8 times per electrode</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>9 times per electrode</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>10 times per electrode</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>11 times per electrode</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>12 times per electrode</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>13 times per electrode</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>14 times per electrode</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>15 times per electrode</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>16 times per electrode</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>17 times per electrode</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>18 times per electrode</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>19 times per electrode</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>20 times per electrode</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>21 times per electrode</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>22 times per electrode</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>23 times per electrode</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>24 times per electrode</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11000</name>
<description>25 times per electrode</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>11001</name>
<description>26 times per electrode</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>27 times per electrode</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>28 times per electrode</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11100</name>
<description>29 times per electrode</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>30 times per electrode</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>31 times per electrode</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>32 times per electrode</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PS</name>
<description>PS</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Electrode Oscillator Frequency divided by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Electrode Oscillator Frequency divided by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Electrode Oscillator Frequency divided by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Electrode Oscillator Frequency divided by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Electrode Oscillator Frequency divided by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Electrode Oscillator Frequency divided by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Electrode Oscillator Frequency divided by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Electrode Oscillator Frequency divided by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTCHRG</name>
<description>EXTCHRG</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>500 nA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>1 uA.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 uA.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>4 uA.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>8 uA.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>16 uA.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>32 uA.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>64 uA.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DVOLT</name>
<description>DVOLT</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>DV = 1.03 V; VP = 1.33 V; Vm = 0.30 V.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>DV = 0.73 V; VP = 1.18 V; Vm = 0.45 V.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>DV = 0.43 V; VP = 1.03 V; Vm = 0.60 V.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>DV = 0.29 V; VP = 0.95 V; Vm = 0.67 V.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REFCHRG</name>
<description>REFCHRG</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>500 nA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>1 uA.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 uA.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>4 uA.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>8 uA.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>16 uA.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>32 uA.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>64 uA.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>TSI analog modes setup and status bits.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Set TSI in capacitive sensing(non-noise detection) mode.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Set TSI analog to work in automatic noise detection mode.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ESOR</name>
<description>End-of-scan or Out-of-Range Interrupt Selection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Out-of-range interrupt is allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>End-of-scan interrupt is allowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTRGF</name>
<description>Out of Range Flag.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>TSI DATA Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSICNT</name>
<description>TSI Conversion Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SWTS</name>
<description>Software Trigger Start</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start a scan to determine which channel is specified by TSI_DATA[TSICH].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Transfer Enabled</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSICH</name>
<description>TSICH</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Channel 0.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Channel 1.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Channel 2.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Channel 3.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Channel 4.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Channel 5.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Channel 6.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Channel 7.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Channel 8.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Channel 9.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Channel 10.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Channel 11.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Channel 12.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Channel 13.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Channel 14.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Channel 15.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSHD</name>
<description>TSI Threshold Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>THRESL</name>
<description>TSI Wakeup Channel Low-threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>THRESH</name>
<description>TSI Wakeup Channel High-threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SIM</name>
<description>System Integration Module</description>
<prependToName>SIM_</prependToName>
<baseAddress>0x40047000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1108</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SOPT1</name>
<description>System Options Register 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OSC32KSEL</name>
<description>32K Oscillator Clock Select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>System oscillator (OSC32KCLK)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>RTC_CLKIN</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>LPO 1kHz</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBVSTBY</name>
<description>USB voltage regulator in standby mode during VLPR and VLPW modes</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB voltage regulator not in standby during VLPR and VLPW modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB voltage regulator in standby during VLPR and VLPW modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBSSTBY</name>
<description>USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBREGEN</name>
<description>USB voltage regulator enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB voltage regulator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB voltage regulator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT1CFG</name>
<description>SOPT1 Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>URWE</name>
<description>USB voltage regulator enable write enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SOPT1 USBREGEN cannot be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SOPT1 USBREGEN can be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UVSWE</name>
<description>USB voltage regulator VLP standby write enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SOPT1 USBVSTB cannot be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SOPT1 USBVSTB can be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USSWE</name>
<description>USB voltage regulator stop standby write enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SOPT1 USBSSTB cannot be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SOPT1 USBSSTB can be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT2</name>
<description>System Options Register 2</description>
<addressOffset>0x1004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTCCLKOUTSEL</name>
<description>RTC Clock Out Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RTC 1 Hz clock is output on the RTC_CLKOUT pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OSCERCLK clock is output on the RTC_CLKOUT pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKOUTSEL</name>
<description>CLKOUT select</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>010</name>
<description>Bus clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>LPO clock (1 kHz)</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>MCGIRCLK</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>OSCERCLK</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLFLLSEL</name>
<description>PLL/FLL clock select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGFLLCLK clock</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGPLLCLK clock with fixed divide by 2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBSRC</name>
<description>USB clock source select</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External bypass clock (USB_CLKIN).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGFLLCLK clock , or MCGPLLCLK/2 clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPMSRC</name>
<description>TPM Clock Source Select</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Clock disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCGFLLCLK clock , or MCGPLLCLK/2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>OSCERCLK clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCGIRCLK clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0SRC</name>
<description>UART0 Clock Source Select</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Clock disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCGFLLCLK clock , or MCGPLLCLK/2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>OSCERCLK clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCGIRCLK clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT4</name>
<description>System Options Register 4</description>
<addressOffset>0x100C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TPM1CH0SRC</name>
<description>TPM1 channel 0 input capture source select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>TPM1_CH0 signal</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>USB start of frame pulse</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM2CH0SRC</name>
<description>TPM2 Channel 0 Input Capture Source Select</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM2_CH0 signal</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM0CLKSEL</name>
<description>TPM0 External Clock Pin Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM0 external clock driven by TPM_CLKIN0 pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM0 external clock driven by TPM_CLKIN1 pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM1CLKSEL</name>
<description>TPM1 External Clock Pin Select</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM1 external clock driven by TPM_CLKIN0 pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM1 external clock driven by TPM_CLKIN1 pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM2CLKSEL</name>
<description>TPM2 External Clock Pin Select</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM2 external clock driven by TPM_CLKIN0 pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TPM2 external clock driven by TPM_CLKIN1 pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT5</name>
<description>System Options Register 5</description>
<addressOffset>0x1010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UART0TXSRC</name>
<description>UART0 Transmit Data Source Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART0_TX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>UART0_TX pin modulated with TPM1 channel 0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>UART0_TX pin modulated with TPM2 channel 0 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0RXSRC</name>
<description>UART0 Receive Data Source Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART_RX pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1TXSRC</name>
<description>UART1 Transmit Data Source Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART1_TX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>UART1_TX pin modulated with TPM1 channel 0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>UART1_TX pin modulated with TPM2 channel 0 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1RXSRC</name>
<description>UART1 Receive Data Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART1_RX pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0ODE</name>
<description>UART0 Open Drain Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain is disabled on UART0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain is enabled on UART0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1ODE</name>
<description>UART1 Open Drain Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain is disabled on UART1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain is enabled on UART1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART2ODE</name>
<description>UART2 Open Drain Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain is disabled on UART2</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain is enabled on UART2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT7</name>
<description>System Options Register 7</description>
<addressOffset>0x1018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADC0TRGSEL</name>
<description>ADC0 Trigger Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>External trigger pin input (EXTRG_IN)</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>CMP0 output</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>PIT trigger 0</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>PIT trigger 1</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>TPM0 overflow</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>TPM1 overflow</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>TPM2 overflow</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>RTC alarm</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>RTC seconds</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>LPTMR0 trigger</description>
<value>#1110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0PRETRGSEL</name>
<description>ADC0 Pretrigger Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pre-trigger A</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pre-trigger B</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0ALTTRGEN</name>
<description>ADC0 Alternate Trigger Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Alternate trigger selected for ADC0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDID</name>
<description>System Device Identification Register</description>
<addressOffset>0x1024</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x100500</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PINID</name>
<description>Pincount Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>16-pin</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>24-pin</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>32-pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>36-pin</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>48-pin</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>64-pin</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>80-pin</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>100-pin</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Custom pinout (WLCSP)</description>
<value>#1011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIEID</name>
<description>Device Die Number</description>
<bitOffset>7</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
<field>
<name>REVID</name>
<description>Device Revision Number</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRAMSIZE</name>
<description>System SRAM Size</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>0.5 KB</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>1 KB</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>2 KB</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>4 KB</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>8 KB</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>16 KB</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>32 KB</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>64 KB</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SERIESID</name>
<description>Kinetis Series ID</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>KL family</description>
<value>#0001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUBFAMID</name>
<description>Kinetis Sub-Family ID</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0010</name>
<description>KLx2 Subfamily</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>KLx3 Subfamily</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>KLx4 Subfamily</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>KLx5 Subfamily</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>KLx6 Subfamily</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>KLx7 Subfamily</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAMID</name>
<description>Kinetis family ID</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>KL0x Family (low end)</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>KL1x Family (basic)</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>KL2x Family (USB)</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>KL3x Family (Segment LCD)</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>KL4x Family (USB and Segment LCD)</description>
<value>#0100</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC4</name>
<description>System Clock Gating Control Register 4</description>
<addressOffset>0x1034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0000030</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2C0</name>
<description>I2C0 Clock Gate Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>I2C1 Clock Gate Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0</name>
<description>UART0 Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1</name>
<description>UART1 Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART2</name>
<description>UART2 Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBOTG</name>
<description>USB Clock Gate Control</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP</name>
<description>Comparator Clock Gate Control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0</name>
<description>SPI0 Clock Gate Control</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1</name>
<description>SPI1 Clock Gate Control</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC5</name>
<description>System Clock Gating Control Register 5</description>
<addressOffset>0x1038</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x182</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPTMR</name>
<description>Low Power Timer Access Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Access disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSI</name>
<description>TSI Access Control</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Access disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTA</name>
<description>Port A Clock Gate Control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTB</name>
<description>Port B Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTC</name>
<description>Port C Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTD</name>
<description>Port D Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTE</name>
<description>Port E Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC6</name>
<description>System Clock Gating Control Register 6</description>
<addressOffset>0x103C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTF</name>
<description>Flash Memory Clock Gate Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX</name>
<description>DMA Mux Clock Gate Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2S</name>
<description>I2S Clock Gate Control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIT</name>
<description>PIT Clock Gate Control</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM0</name>
<description>TPM0 Clock Gate Control</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM1</name>
<description>TPM1 Clock Gate Control</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPM2</name>
<description>TPM2 Clock Gate Control</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0</name>
<description>ADC0 Clock Gate Control</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC</name>
<description>RTC Access Control</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Access and interrupts disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access and interrupts enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC0</name>
<description>DAC0 Clock Gate Control</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC7</name>
<description>System Clock Gating Control Register 7</description>
<addressOffset>0x1040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Clock Gate Control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV1</name>
<description>System Clock Divider Register 1</description>
<addressOffset>0x1044</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUTDIV4</name>
<description>Clock 4 Output Divider value</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide-by-1.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide-by-2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide-by-3.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide-by-4.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide-by-5.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide-by-6.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide-by-7.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide-by-8.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTDIV1</name>
<description>Clock 1 Output Divider value</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Divide-by-1.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Divide-by-2.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Divide-by-3.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Divide-by-4.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Divide-by-5.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Divide-by-6.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Divide-by-7.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Divide-by-8.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Divide-by-9.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Divide-by-10.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Divide-by-11.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Divide-by-12.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Divide-by-13.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Divide-by-14.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Divide-by-15.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Divide-by-16.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG1</name>
<description>Flash Configuration Register 1</description>
<addressOffset>0x104C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLASHDIS</name>
<description>Flash Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHDOZE</name>
<description>Flash Doze</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash remains enabled during Doze mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled for the duration of Doze mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFSIZE</name>
<description>Program Flash Size</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>8 KB of program flash memory, 0.25 KB protection region</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>16 KB of program flash memory, 0.5 KB protection region</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>32 KB of program flash memory, 1 KB protection region</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>64 KB of program flash memory, 2 KB protection region</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>128 KB of program flash memory, 4 KB protection region</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>256 KB of program flash memory, 8 KB protection region</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>128 KB of program flash memory, 4 KB protection region 256 KB of program flash memory, 8 KB protection region</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG2</name>
<description>Flash Configuration Register 2</description>
<addressOffset>0x1050</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x7FFF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAXADDR1</name>
<description>This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1)</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MAXADDR0</name>
<description>Max Address lock</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDMH</name>
<description>Unique Identification Register Mid-High</description>
<addressOffset>0x1058</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDML</name>
<description>Unique Identification Register Mid Low</description>
<addressOffset>0x105C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDL</name>
<description>Unique Identification Register Low</description>
<addressOffset>0x1060</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>COPC</name>
<description>COP Control Register</description>
<addressOffset>0x1100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COPW</name>
<description>COP Windowed Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowed mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COPCLKS</name>
<description>COP Clock Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 1 kHz clock is source to COP.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus clock is source to COP.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COPT</name>
<description>COP Watchdog Timeout</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>COP disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>COP timeout after 25 LPO cycles or 213 bus clock cycles</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>COP timeout after 28 LPO cycles or 216 bus clock cycles</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>COP timeout after 210 LPO cycles or 218 bus clock cycles</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRVCOP</name>
<description>Service COP</description>
<addressOffset>0x1104</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SRVCOP</name>
<description>Service COP Register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTA</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTA_</prependToName>
<baseAddress>0x40049000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTA</name>
<value>30</value>
</interrupt>
<registers>
<register>
<name>PCR0</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x706</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR1</name>
<description>Pin Control Register n</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR2</name>
<description>Pin Control Register n</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR3</name>
<description>Pin Control Register n</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x703</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR4</name>
<description>Pin Control Register n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x707</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR5</name>
<description>Pin Control Register n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR6</name>
<description>Pin Control Register n</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR7</name>
<description>Pin Control Register n</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR8</name>
<description>Pin Control Register n</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR9</name>
<description>Pin Control Register n</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR10</name>
<description>Pin Control Register n</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR11</name>
<description>Pin Control Register n</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR12</name>
<description>Pin Control Register n</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR13</name>
<description>Pin Control Register n</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR14</name>
<description>Pin Control Register n</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR15</name>
<description>Pin Control Register n</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR16</name>
<description>Pin Control Register n</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR17</name>
<description>Pin Control Register n</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR18</name>
<description>Pin Control Register n</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR19</name>
<description>Pin Control Register n</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR20</name>
<description>Pin Control Register n</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x717</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR21</name>
<description>Pin Control Register n</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR22</name>
<description>Pin Control Register n</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR23</name>
<description>Pin Control Register n</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR24</name>
<description>Pin Control Register n</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR25</name>
<description>Pin Control Register n</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR26</name>
<description>Pin Control Register n</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR27</name>
<description>Pin Control Register n</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR28</name>
<description>Pin Control Register n</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR29</name>
<description>Pin Control Register n</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR30</name>
<description>Pin Control Register n</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR31</name>
<description>Pin Control Register n</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTB</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTB_</prependToName>
<baseAddress>0x4004A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCR0</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR1</name>
<description>Pin Control Register n</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR2</name>
<description>Pin Control Register n</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR3</name>
<description>Pin Control Register n</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR4</name>
<description>Pin Control Register n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR5</name>
<description>Pin Control Register n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR6</name>
<description>Pin Control Register n</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR7</name>
<description>Pin Control Register n</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR8</name>
<description>Pin Control Register n</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR9</name>
<description>Pin Control Register n</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR10</name>
<description>Pin Control Register n</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR11</name>
<description>Pin Control Register n</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR12</name>
<description>Pin Control Register n</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR13</name>
<description>Pin Control Register n</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR14</name>
<description>Pin Control Register n</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR15</name>
<description>Pin Control Register n</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR16</name>
<description>Pin Control Register n</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR17</name>
<description>Pin Control Register n</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR18</name>
<description>Pin Control Register n</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR19</name>
<description>Pin Control Register n</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR20</name>
<description>Pin Control Register n</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR21</name>
<description>Pin Control Register n</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR22</name>
<description>Pin Control Register n</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR23</name>
<description>Pin Control Register n</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR24</name>
<description>Pin Control Register n</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR25</name>
<description>Pin Control Register n</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR26</name>
<description>Pin Control Register n</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR27</name>
<description>Pin Control Register n</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR28</name>
<description>Pin Control Register n</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR29</name>
<description>Pin Control Register n</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR30</name>
<description>Pin Control Register n</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR31</name>
<description>Pin Control Register n</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTC</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTC_</prependToName>
<baseAddress>0x4004B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC_PORTD</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>PCR0</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR1</name>
<description>Pin Control Register n</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR2</name>
<description>Pin Control Register n</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR3</name>
<description>Pin Control Register n</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR4</name>
<description>Pin Control Register n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR5</name>
<description>Pin Control Register n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR6</name>
<description>Pin Control Register n</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR7</name>
<description>Pin Control Register n</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR8</name>
<description>Pin Control Register n</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR9</name>
<description>Pin Control Register n</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR10</name>
<description>Pin Control Register n</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR11</name>
<description>Pin Control Register n</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR12</name>
<description>Pin Control Register n</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR13</name>
<description>Pin Control Register n</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR14</name>
<description>Pin Control Register n</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR15</name>
<description>Pin Control Register n</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR16</name>
<description>Pin Control Register n</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR17</name>
<description>Pin Control Register n</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR18</name>
<description>Pin Control Register n</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR19</name>
<description>Pin Control Register n</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR20</name>
<description>Pin Control Register n</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR21</name>
<description>Pin Control Register n</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR22</name>
<description>Pin Control Register n</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR23</name>
<description>Pin Control Register n</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR24</name>
<description>Pin Control Register n</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR25</name>
<description>Pin Control Register n</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR26</name>
<description>Pin Control Register n</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR27</name>
<description>Pin Control Register n</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR28</name>
<description>Pin Control Register n</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR29</name>
<description>Pin Control Register n</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR30</name>
<description>Pin Control Register n</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR31</name>
<description>Pin Control Register n</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTD</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTD_</prependToName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC_PORTD</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>PCR0</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR1</name>
<description>Pin Control Register n</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR2</name>
<description>Pin Control Register n</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR3</name>
<description>Pin Control Register n</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR4</name>
<description>Pin Control Register n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR5</name>
<description>Pin Control Register n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR6</name>
<description>Pin Control Register n</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR7</name>
<description>Pin Control Register n</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR8</name>
<description>Pin Control Register n</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR9</name>
<description>Pin Control Register n</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR10</name>
<description>Pin Control Register n</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR11</name>
<description>Pin Control Register n</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR12</name>
<description>Pin Control Register n</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR13</name>
<description>Pin Control Register n</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR14</name>
<description>Pin Control Register n</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR15</name>
<description>Pin Control Register n</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR16</name>
<description>Pin Control Register n</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR17</name>
<description>Pin Control Register n</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR18</name>
<description>Pin Control Register n</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR19</name>
<description>Pin Control Register n</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR20</name>
<description>Pin Control Register n</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR21</name>
<description>Pin Control Register n</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR22</name>
<description>Pin Control Register n</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR23</name>
<description>Pin Control Register n</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR24</name>
<description>Pin Control Register n</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR25</name>
<description>Pin Control Register n</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR26</name>
<description>Pin Control Register n</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR27</name>
<description>Pin Control Register n</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR28</name>
<description>Pin Control Register n</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR29</name>
<description>Pin Control Register n</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR30</name>
<description>Pin Control Register n</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR31</name>
<description>Pin Control Register n</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTE</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTE_</prependToName>
<baseAddress>0x4004D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCR0</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR1</name>
<description>Pin Control Register n</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR2</name>
<description>Pin Control Register n</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR3</name>
<description>Pin Control Register n</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR4</name>
<description>Pin Control Register n</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR5</name>
<description>Pin Control Register n</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR6</name>
<description>Pin Control Register n</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR7</name>
<description>Pin Control Register n</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR8</name>
<description>Pin Control Register n</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR9</name>
<description>Pin Control Register n</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR10</name>
<description>Pin Control Register n</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR11</name>
<description>Pin Control Register n</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR12</name>
<description>Pin Control Register n</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR13</name>
<description>Pin Control Register n</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR14</name>
<description>Pin Control Register n</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR15</name>
<description>Pin Control Register n</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR16</name>
<description>Pin Control Register n</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR17</name>
<description>Pin Control Register n</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR18</name>
<description>Pin Control Register n</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR19</name>
<description>Pin Control Register n</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR20</name>
<description>Pin Control Register n</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR21</name>
<description>Pin Control Register n</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR22</name>
<description>Pin Control Register n</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR23</name>
<description>Pin Control Register n</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR24</name>
<description>Pin Control Register n</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR25</name>
<description>Pin Control Register n</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR26</name>
<description>Pin Control Register n</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR27</name>
<description>Pin Control Register n</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR28</name>
<description>Pin Control Register n</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR29</name>
<description>Pin Control Register n</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR30</name>
<description>Pin Control Register n</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCR31</name>
<description>Pin Control Register n</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCG</name>
<description>Multipurpose Clock Generator module</description>
<prependToName>MCG_</prependToName>
<baseAddress>0x40064000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MCG</name>
<value>27</value>
</interrupt>
<registers>
<register>
<name>C1</name>
<description>MCG Control 1 Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IREFSTEN</name>
<description>Internal Reference Stop Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRCLKEN</name>
<description>Internal Reference Clock Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGIRCLK inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGIRCLK active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFS</name>
<description>Internal Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slow internal reference clock is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRDIV</name>
<description>FLL External Reference Divider</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 .</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 .</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - Reserved.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>MCG Control 2 Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCS</name>
<description>Internal Reference Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slow internal reference clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fast internal reference clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LP</name>
<description>Low Power Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL or PLL is not disabled in bypass modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FLL or PLL is disabled in bypass modes (lower power)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFS0</name>
<description>External Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock requested.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Oscillator requested.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HGO0</name>
<description>High Gain Oscillator Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configure crystal oscillator for low-power operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configure crystal oscillator for high-gain operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RANGE0</name>
<description>Frequency Range Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low frequency range selected for the crystal oscillator .</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - High frequency range selected for the crystal oscillator .</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>1X</name>
<description>Encoding 2 - Very high frequency range selected for the crystal oscillator .</description>
<value>#1x</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCFTRIM</name>
<description>Fast Internal Reference Clock Fine Trim</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOCRE0</name>
<description>Loss of Clock Reset Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a loss of OSC0 external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a loss of OSC0 external reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>MCG Control 3 Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SCTRIM</name>
<description>Slow Internal Reference Clock Trim Setting</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>MCG Control 4 Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xE0</resetMask>
<fields>
<field>
<name>SCFTRIM</name>
<description>Slow Internal Reference Clock Fine Trim</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCTRIM</name>
<description>Fast Internal Reference Clock Trim Setting</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DRST_DRS</name>
<description>DCO Range Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low range (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Mid range.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - Mid-high range.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - High range.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMX32</name>
<description>DCO Maximum Frequency with 32.768 kHz Reference</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DCO has a default range of 25%.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DCO is fine-tuned for maximum frequency with 32.768 kHz reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>MCG Control 5 Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PRDIV0</name>
<description>PLL External Reference Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Divide Factor is 1</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Divide Factor is 2</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Divide Factor is 3</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Divide Factor is 4</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Divide Factor is 5</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>Divide Factor is 6</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Divide Factor is 7</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Divide Factor is 8</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>8</name>
<description>Divide Factor is 9</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>9</name>
<description>Divide Factor is 10</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Divide Factor is 11</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Divide Factor is 12</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>12</name>
<description>Divide Factor is 13</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>13</name>
<description>Divide Factor is 14</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>14</name>
<description>Divide Factor is 15</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>15</name>
<description>Divide Factor is 16</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>16</name>
<description>Divide Factor is 17</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>17</name>
<description>Divide Factor is 18</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>18</name>
<description>Divide Factor is 19</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>19</name>
<description>Divide Factor is 20</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>20</name>
<description>Divide Factor is 21</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>21</name>
<description>Divide Factor is 22</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>22</name>
<description>Divide Factor is 23</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>23</name>
<description>Divide Factor is 24</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>24</name>
<description>Divide Factor is 25</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>25</name>
<description>Divide Factor is 26</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>26</name>
<description>Divide Factor is 27</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>27</name>
<description>Divide Factor is 28</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>28</name>
<description>Divide Factor is 29</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>29</name>
<description>Divide Factor is 30</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>30</name>
<description>Divide Factor is 31</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>31</name>
<description>Divide Factor is 32</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLSTEN0</name>
<description>PLL Stop Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGPLLCLK is disabled in any of the Stop modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGPLLCLK is enabled if system is in Normal Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLCLKEN0</name>
<description>PLL Clock Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGPLLCLK is inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGPLLCLK is active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C6</name>
<description>MCG Control 6 Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VDIV0</name>
<description>VCO 0 Divider</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Multiply Factor is 24</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Multiply Factor is 25</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Multiply Factor is 26</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Multiply Factor is 27</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Multiply Factor is 28</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>Multiply Factor is 29</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Multiply Factor is 30</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Multiply Factor is 31</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>8</name>
<description>Multiply Factor is 32</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>9</name>
<description>Multiply Factor is 33</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Multiply Factor is 34</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Multiply Factor is 35</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>12</name>
<description>Multiply Factor is 36</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>13</name>
<description>Multiply Factor is 37</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>14</name>
<description>Multiply Factor is 38</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>15</name>
<description>Multiply Factor is 39</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>16</name>
<description>Multiply Factor is 40</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>17</name>
<description>Multiply Factor is 41</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>18</name>
<description>Multiply Factor is 42</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>19</name>
<description>Multiply Factor is 43</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>20</name>
<description>Multiply Factor is 44</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>21</name>
<description>Multiply Factor is 45</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>22</name>
<description>Multiply Factor is 46</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>23</name>
<description>Multiply Factor is 47</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>24</name>
<description>Multiply Factor is 48</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>25</name>
<description>Multiply Factor is 49</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>26</name>
<description>Multiply Factor is 50</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>27</name>
<description>Multiply Factor is 51</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>28</name>
<description>Multiply Factor is 52</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>29</name>
<description>Multiply Factor is 53</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>30</name>
<description>Multiply Factor is 54</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>31</name>
<description>Multiply Factor is 55</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CME0</name>
<description>Clock Monitor Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External clock monitor is disabled for OSC0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock monitor is enabled for OSC0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLS</name>
<description>PLL Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOLIE0</name>
<description>Loss of Lock Interrrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt request is generated on loss of lock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate an interrupt request on loss of lock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>MCG Status Register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCST</name>
<description>Internal Reference Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of internal reference clock is the slow clock (32 kHz IRC).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of internal reference clock is the fast clock (4 MHz IRC).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCINIT0</name>
<description>OSC Initialization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CLKST</name>
<description>Clock Mode Status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of the FLL is selected (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - Output of the PLL is selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFST</name>
<description>Internal Reference Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of FLL reference clock is the external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of FLL reference clock is the internal reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLST</name>
<description>PLL Select Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of PLLS clock is FLL clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of PLLS clock is PLL output clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK0</name>
<description>Lock Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL is currently unlocked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is currently locked.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOLS0</name>
<description>Loss of Lock Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL has not lost lock since LOLS 0 was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL has lost lock since LOLS 0 was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC</name>
<description>MCG Status and Control Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCS0</name>
<description>OSC0 Loss of Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loss of OSC0 has not occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of OSC0 has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCRDIV</name>
<description>Fast Clock Internal Reference Divider</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide Factor is 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide Factor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide Factor is 4.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide Factor is 8.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide Factor is 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide Factor is 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide Factor is 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide Factor is 128.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLTPRSRV</name>
<description>FLL Filter Preserve Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL filter and FLL frequency will reset on changes to currect clock mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fll filter and FLL frequency retain their previous values during new clock mode change.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMF</name>
<description>Automatic Trim Machine Fail Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Automatic Trim Machine completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Automatic Trim Machine failed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMS</name>
<description>Automatic Trim Machine Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>32 kHz Internal Reference Clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>4 MHz Internal Reference Clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATME</name>
<description>Automatic Trim Machine Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto Trim Machine disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto Trim Machine enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ATCVH</name>
<description>MCG Auto Trim Compare Value High Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVH</name>
<description>ATM Compare Value High</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATCVL</name>
<description>MCG Auto Trim Compare Value Low Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVL</name>
<description>ATM Compare Value Low</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C7</name>
<description>MCG Control 7 Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OSCSEL</name>
<description>MCG OSC Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects System Oscillator (OSCCLK).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Selects 32 kHz RTC Oscillator.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C8</name>
<description>MCG Control 8 Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOLRE</name>
<description>PLL Loss of Lock Reset Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a PLL loss of lock indication.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C9</name>
<description>MCG Control 9 Register</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>C10</name>
<description>MCG Control 10 Register</description>
<addressOffset>0xF</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>OSC0</name>
<description>Oscillator</description>
<prependToName>OSC0_</prependToName>
<baseAddress>0x40065000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<description>OSC Control Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SC16P</name>
<description>Oscillator 16 pF Capacitor Load Configure</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 16 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC8P</name>
<description>Oscillator 8 pF Capacitor Load Configure</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 8 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC4P</name>
<description>Oscillator 4 pF Capacitor Load Configure</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 4 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC2P</name>
<description>Oscillator 2 pF Capacitor Load Configure</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 2 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFSTEN</name>
<description>External Reference Stop Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERCLKEN</name>
<description>External Reference Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C0_</prependToName>
<baseAddress>0x40066000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0</name>
<value>8</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Most significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Least significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C1_</prependToName>
<baseAddress>0x40067000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1</name>
<value>9</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Most significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Least significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART0</name>
<description>Universal Asynchronous Receiver/Transmitter</description>
<prependToName>UART0_</prependToName>
<baseAddress>0x4006A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0</name>
<value>12</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Register High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SBNS</name>
<description>Stop Bit Number Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One stop bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Two stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIE</name>
<description>RX Input Active Edge Interrupt Enable (for RXEDGIF)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Register Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No hardware parity generation or checking.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle-line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address-mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-Bit or 8-Bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver and transmitter use 8-bit data characters.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 9-bit data characters.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART_RX pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single-wire UART mode where the UART_TX pin is connected to the transmitter output and receiver input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOZEEN</name>
<description>Doze Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART is enabled in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART is disabled in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation - UART_RX and UART_TX use separate pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART_RX pin is not used by UART.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break character(s) to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal UART receiver operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver in standby waiting for wakeup condition.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable for IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from IDLE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when IDLE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Interrupt Enable for RDRF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RDRF disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when RDRF flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable for TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TC disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TC flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmit Interrupt Enable for TDRE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TDRE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TDRE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected. This does not guarantee the framing is correct.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Noise detected in the received character in UART_D.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive overrun (new UART data lost).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No idle line detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle line was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data buffer empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data buffer full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmission Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data buffer full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data buffer empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active ( UART_RXD input not idle).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Character Generation Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wake Up Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>MSB First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>UART_RX Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character has been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character has been detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when PF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when FE is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when NF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when OR is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>UART_TX Pin Direction in Single-Wire Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART_TXD pin is an input in single-wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART_TXD pin is an output in single-wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>R9T8</name>
<description>Receive Bit 9 / Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8T9</name>
<description>Receive Bit 8 / Transmit Bit 9</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>R0T0</name>
<description>Read receive data buffer 0 or write transmit data buffer 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R1T1</name>
<description>Read receive data buffer 1 or write transmit data buffer 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R2T2</name>
<description>Read receive data buffer 2 or write transmit data buffer 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R3T3</name>
<description>Read receive data buffer 3 or write transmit data buffer 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R4T4</name>
<description>Read receive data buffer 4 or write transmit data buffer 4.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R5T5</name>
<description>Read receive data buffer 5 or write transmit data buffer 5.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R6T6</name>
<description>Read receive data buffer 6 or write transmit data buffer 6.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R7T7</name>
<description>Read receive data buffer 7 or write transmit data buffer 7.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OSR</name>
<description>Over Sampling Ratio</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver and transmitter use 8-bit or 9-bit data characters.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 10-bit data characters.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RESYNCDIS</name>
<description>Resynchronization Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Resynchronization during received data word is supported</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Resynchronization during received data word is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOTHEDGE</name>
<description>Both Edge Sampling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAE</name>
<description>Receiver Full DMA Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAE</name>
<description>Transmitter DMA Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART1</name>
<description>Universal Asynchronous Receiver/Transmitter (UART)</description>
<groupName>UART</groupName>
<prependToName>UART1_</prependToName>
<baseAddress>0x4006B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART1</name>
<value>13</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Register: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SBNS</name>
<description>Stop Bit Number Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One stop bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Two stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable (for RXEDGIF)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Register: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No hardware parity generation or checking.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle-line wake-up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address-mark wake-up.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-Bit or 8-Bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal - start + 8 data bits (lsb first) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTSWAI</name>
<description>UART Stops in Wait Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART clocks freeze while CPU is in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation - RxD and TxD use separate pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break character(s) to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal UART receiver operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver in standby waiting for wake-up condition.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable for IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from S1[IDLE] disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when S1[IDLE] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Interrupt Enable for RDRF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from S1[RDRF] disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when S1[RDRF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable for TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TC disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TC flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmit Interrupt Enable for TDRE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TDRE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TDRE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected. This does not guarantee the framing is correct.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Noise detected in the received character in UART_D.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive overrun (new UART data lost).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No idle line detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle line was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data register empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data register full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmission Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data register (buffer) full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data register (buffer) empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active (RxD input not idle).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break detection is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Character Generation Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wake Up Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character has been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character has been detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when PF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when FE is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when NF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when OR is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>TxD Pin Direction in Single-Wire Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TxD pin is an input in single-wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TxD pin is an output in single-wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Ninth Data Bit for Transmitter</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Ninth Data Bit for Receiver</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>R0T0</name>
<description>Read receive data buffer 0 or write transmit data buffer 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R1T1</name>
<description>Read receive data buffer 1 or write transmit data buffer 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R2T2</name>
<description>Read receive data buffer 2 or write transmit data buffer 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R3T3</name>
<description>Read receive data buffer 3 or write transmit data buffer 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R4T4</name>
<description>Read receive data buffer 4 or write transmit data buffer 4.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R5T5</name>
<description>Read receive data buffer 5 or write transmit data buffer 5.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R6T6</name>
<description>Read receive data buffer 6 or write transmit data buffer 6.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R7T7</name>
<description>Read receive data buffer 7 or write transmit data buffer 7.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART2</name>
<description>Universal Asynchronous Receiver/Transmitter (UART)</description>
<groupName>UART</groupName>
<prependToName>UART2_</prependToName>
<baseAddress>0x4006C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART2</name>
<value>14</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Register: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SBNS</name>
<description>Stop Bit Number Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One stop bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Two stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable (for RXEDGIF)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Register: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No hardware parity generation or checking.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle-line wake-up.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address-mark wake-up.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-Bit or 8-Bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal - start + 8 data bits (lsb first) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTSWAI</name>
<description>UART Stops in Wait Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART clocks freeze while CPU is in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation - RxD and TxD use separate pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break character(s) to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal UART receiver operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver in standby waiting for wake-up condition.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable for IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from S1[IDLE] disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when S1[IDLE] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Interrupt Enable for RDRF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from S1[RDRF] disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when S1[RDRF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable for TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TC disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TC flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmit Interrupt Enable for TDRE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TDRE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TDRE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected. This does not guarantee the framing is correct.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Noise detected in the received character in UART_D.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive overrun (new UART data lost).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No idle line detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle line was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data register empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data register full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmission Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data register (buffer) full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data register (buffer) empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active (RxD input not idle).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break detection is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Character Generation Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wake Up Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character has been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character has been detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when PF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when FE is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when NF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when OR is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>TxD Pin Direction in Single-Wire Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TxD pin is an input in single-wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TxD pin is an output in single-wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Ninth Data Bit for Transmitter</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Ninth Data Bit for Receiver</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>R0T0</name>
<description>Read receive data buffer 0 or write transmit data buffer 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R1T1</name>
<description>Read receive data buffer 1 or write transmit data buffer 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R2T2</name>
<description>Read receive data buffer 2 or write transmit data buffer 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R3T3</name>
<description>Read receive data buffer 3 or write transmit data buffer 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R4T4</name>
<description>Read receive data buffer 4 or write transmit data buffer 4.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R5T5</name>
<description>Read receive data buffer 5 or write transmit data buffer 5.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R6T6</name>
<description>Read receive data buffer 6 or write transmit data buffer 6.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R7T7</name>
<description>Read receive data buffer 7 or write transmit data buffer 7.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USB0</name>
<description>Universal Serial Bus, OTG Capable Controller</description>
<prependToName>USB0_</prependToName>
<baseAddress>0x40072000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x115</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USB0</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>PERID</name>
<description>Peripheral ID register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ID</name>
<description>Peripheral Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IDCOMP</name>
<description>Peripheral ID Complement register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFB</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>NID</name>
<description>Ones complement of peripheral identification bits.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>REV</name>
<description>Peripheral Revision register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x33</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>REV</name>
<description>Revision</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ADDINFO</name>
<description>Peripheral Additional Info register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IEHOST</name>
<description>When this bit is set, the USB peripheral is operating in host mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IRQNUM</name>
<description>Assigned Interrupt Request Number</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OTGISTAT</name>
<description>OTG Interrupt Status register</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVBUSCHG</name>
<description>This bit is set when a change in VBUS is detected on an A device.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>B_SESS_CHG</name>
<description>This bit is set when a change in VBUS is detected on a B device.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SESSVLDCHG</name>
<description>This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LINE_STATE_CHG</name>
<description>This bit is set when the USB line state changes</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ONEMSEC</name>
<description>This bit is set when the 1 millisecond timer expires</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IDCHG</name>
<description>This bit is set when a change in the ID Signal from the USB connector is sensed.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTGICR</name>
<description>OTG Interrupt Control register</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVBUSEN</name>
<description>A VBUS Valid Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the AVBUSCHG interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the AVBUSCHG interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSESSEN</name>
<description>B Session END Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the B_SESS_CHG interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the B_SESS_CHG interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SESSVLDEN</name>
<description>Session Valid Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the SESSVLDCHG interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the SESSVLDCHG interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINESTATEEN</name>
<description>Line State Change Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the LINE_STAT_CHG interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the LINE_STAT_CHG interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONEMSECEN</name>
<description>One Millisecond Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Diables the 1ms timer interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the 1ms timer interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDEN</name>
<description>ID Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The ID interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The ID interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OTGSTAT</name>
<description>OTG Status register</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVBUSVLD</name>
<description>A VBUS Valid</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The VBUS voltage is below the A VBUS Valid threshold.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The VBUS voltage is above the A VBUS Valid threshold.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BSESSEND</name>
<description>B Session End</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The VBUS voltage is above the B session end threshold.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The VBUS voltage is below the B session end threshold.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SESS_VLD</name>
<description>Session Valid</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The VBUS voltage is below the B session valid threshold</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The VBUS voltage is above the B session valid threshold.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LINESTATESTABLE</name>
<description>Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The LINE_STAT_CHG bit is not yet stable.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The LINE_STAT_CHG bit has been debounced and is stable.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONEMSECEN</name>
<description>This bit is reserved for the 1ms count, but it is not useful to software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ID</name>
<description>Indicates the current state of the ID pin on the USB connector</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Indicates a Type A cable is plugged into the USB connector.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates no cable is attached or a Type B cable is plugged into the USB connector.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OTGCTL</name>
<description>OTG Control register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OTGEN</name>
<description>On-The-Go pullup/pulldown resistor enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The pull-up and pull-down controls in this register are used.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMLOW</name>
<description>D- Data Line pull-down resistor enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D- pulldown resistor is not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D- pulldown resistor is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPLOW</name>
<description>D+ Data Line pull-down resistor enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D+ pulldown resistor is not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D+ pulldown resistor is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPHIGH</name>
<description>D+ Data Line pullup resistor enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D+ pullup resistor is not enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D+ pullup resistor is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISTAT</name>
<description>Interrupt Status register</description>
<addressOffset>0x80</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>USBRST</name>
<description>This bit is set when the USB Module has decoded a valid USB reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERROR</name>
<description>This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOFTOK</name>
<description>This bit is set when the USB Module receives a Start Of Frame (SOF) token</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOKDNE</name>
<description>This bit is set when the current token being processed has completed</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SLEEP</name>
<description>This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESUME</name>
<description>This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the USB bus</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ATTACH</name>
<description>Attach Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>Stall Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTEN</name>
<description>Interrupt Enable register</description>
<addressOffset>0x84</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>USBRSTEN</name>
<description>USBRST Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the USBRST interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the USBRST interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERROREN</name>
<description>ERROR Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the ERROR interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the ERROR interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOFTOKEN</name>
<description>SOFTOK Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disbles the SOFTOK interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the SOFTOK interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOKDNEEN</name>
<description>TOKDNE Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the TOKDNE interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the TOKDNE interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLEEPEN</name>
<description>SLEEP Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the SLEEP interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the SLEEP interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESUMEEN</name>
<description>RESUME Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the RESUME interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the RESUME interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATTACHEN</name>
<description>ATTACH Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the ATTACH interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the ATTACH interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STALLEN</name>
<description>STALL Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Diasbles the STALL interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the STALL interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ERRSTAT</name>
<description>Error Interrupt Status register</description>
<addressOffset>0x88</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PIDERR</name>
<description>This bit is set when the PID check field fails.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRC5EOF</name>
<description>This error interrupt has two functions</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRC16</name>
<description>This bit is set when a data packet is rejected due to a CRC16 error.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DFN8</name>
<description>This bit is set if the data field received was not 8 bits in length</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTOERR</name>
<description>This bit is set when a bus turnaround timeout error occurs</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAERR</name>
<description>This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTSERR</name>
<description>This bit is set when a bit stuff error is detected</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ERREN</name>
<description>Error Interrupt Enable register</description>
<addressOffset>0x8C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PIDERREN</name>
<description>PIDERR Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the PIDERR interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enters the PIDERR interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC5EOFEN</name>
<description>CRC5/EOF Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the CRC5/EOF interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the CRC5/EOF interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC16EN</name>
<description>CRC16 Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the CRC16 interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the CRC16 interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFN8EN</name>
<description>DFN8 Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the DFN8 interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the DFN8 interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BTOERREN</name>
<description>BTOERR Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the BTOERR interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the BTOERR interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAERREN</name>
<description>DMAERR Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the DMAERR interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the DMAERR interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BTSERREN</name>
<description>BTSERR Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the BTSERR interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the BTSERR interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>Status register</description>
<addressOffset>0x90</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ODD</name>
<description>This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX</name>
<description>Transmit Indicator</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The most recent transaction was a receive operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The most recent transaction was a transmit operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENDP</name>
<description>This four-bit field encodes the endpoint address that received or transmitted the previous token</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTL</name>
<description>Control register</description>
<addressOffset>0x94</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>USBENSOFEN</name>
<description>USB Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disables the USB Module.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the USB Module.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODDRST</name>
<description>Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESUME</name>
<description>When set to 1 this bit enables the USB Module to execute resume signaling</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HOSTMODEEN</name>
<description>When set to 1, this bit enables the USB Module to operate in Host mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESET</name>
<description>Setting this bit enables the USB Module to generate USB reset signaling</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXSUSPENDTOKENBUSY</name>
<description>In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SE0</name>
<description>Live USB Single Ended Zero signal</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JSTATE</name>
<description>Live USB differential receiver JSTATE signal</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description>Address register</description>
<addressOffset>0x98</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>USB Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSEN</name>
<description>Low Speed Enable bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BDTPAGE1</name>
<description>BDT Page register 1</description>
<addressOffset>0x9C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BDTBA</name>
<description>Provides address bits 15 through 9 of the BDT base address.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FRMNUML</name>
<description>Frame Number register Low</description>
<addressOffset>0xA0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FRM</name>
<description>This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FRMNUMH</name>
<description>Frame Number register High</description>
<addressOffset>0xA4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FRM</name>
<description>This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOKEN</name>
<description>Token register</description>
<addressOffset>0xA8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TOKENENDPT</name>
<description>Holds the Endpoint address for the token command</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOKENPID</name>
<description>Contains the token type executed by the USB module.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>OUT Token. USB Module performs an OUT (TX) transaction.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>IN Token. USB Module performs an In (RX) transaction.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>SETUP Token. USB Module performs a SETUP (TX) transaction</description>
<value>#1101</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOFTHLD</name>
<description>SOF Threshold register</description>
<addressOffset>0xAC</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CNT</name>
<description>Represents the SOF count threshold in byte times.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BDTPAGE2</name>
<description>BDT Page Register 2</description>
<addressOffset>0xB0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BDTBA</name>
<description>Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BDTPAGE3</name>
<description>BDT Page Register 3</description>
<addressOffset>0xB4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BDTBA</name>
<description>Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
<name>ENDPT%s</name>
<description>Endpoint Control register</description>
<addressOffset>0xC0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EPHSHK</name>
<description>When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPSTALL</name>
<description>When set this bit indicates that the endpoint is called</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPTXEN</name>
<description>This bit, when set, enables the endpoint for TX transfers.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPRXEN</name>
<description>This bit, when set, enables the endpoint for RX transfers.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPCTLDIS</name>
<description>This bit, when set, disables control (SETUP) transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RETRYDIS</name>
<description>This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HOSTWOHUB</name>
<description>This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBCTRL</name>
<description>USB Control register</description>
<addressOffset>0x100</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PDE</name>
<description>Enables the weak pulldowns on the USB transceiver.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Weak pulldowns are disabled on D+ and D-.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Weak pulldowns are enabled on D+ and D-.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUSP</name>
<description>Places the USB transceiver into the suspend state.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB transceiver is not in suspend state.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB transceiver is in suspend state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OBSERVE</name>
<description>USB OTG Observe register</description>
<addressOffset>0x104</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x50</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMPD</name>
<description>Provides observability of the D- Pulldown signal output from the USB OTG module</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D- pulldown disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D- pulldown enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPPD</name>
<description>Provides observability of the D+ Pulldown . signal output from the USB OTG module</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D+ pulldown disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D+ pulldown enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPPU</name>
<description>Provides observability of the D+ Pullup . signal output from the USB OTG module</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>D+ pullup disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>D+ pullup enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>USB OTG Control register</description>
<addressOffset>0x108</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DPPULLUPNONOTG</name>
<description>Provides control of the DP Pullup in the USB OTG module, if USB is configured in non-OTG device mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DP Pullup in non-OTG device mode is not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DP Pullup in non-OTG device mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>USBTRC0</name>
<description>USB Transceiver Control register 0</description>
<addressOffset>0x10C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>USB_RESUME_INT</name>
<description>USB Asynchronous Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt was generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt was generated because of the USB asynchronous interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNC_DET</name>
<description>Synchronous USB Interrupt Detect</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Synchronous interrupt has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Synchronous interrupt has been detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBRESMEN</name>
<description>Asynchronous Resume Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB asynchronous wakeup from suspend mode disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interupt should only be enabled when the Transceiver is suspended.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBRESET</name>
<description>USB Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal USB module operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Returns the USB module to its reset state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>USBFRMADJUST</name>
<description>Frame Adjust Register</description>
<addressOffset>0x114</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADJ</name>
<description>Frame Adjustment</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP0</name>
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
<prependToName>CMP0_</prependToName>
<baseAddress>0x40073000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP0</name>
<value>16</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>CMP Control Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HYSTCTR</name>
<description>Comparator hard block hysteresis control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Level 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Level 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Level 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Level 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_CNT</name>
<description>Filter Sample Count</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>One sample must agree. The comparator output is simply sampled.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 consecutive samples must agree.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>3 consecutive samples must agree.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>4 consecutive samples must agree.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>5 consecutive samples must agree.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>6 consecutive samples must agree.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>7 consecutive samples must agree.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>CMP Control Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>Comparator Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Analog Comparator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Analog Comparator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPE</name>
<description>Comparator Output Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COS</name>
<description>Comparator Output Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Comparator INVERT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Does not invert the comparator output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverts the comparator output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMODE</name>
<description>Power Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGM</name>
<description>Trigger Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WE</name>
<description>Windowing Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Sample Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sampling mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sampling mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FPR</name>
<description>CMP Filter Period Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>CMP Status and Control Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COUT</name>
<description>Analog Comparator Output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFF</name>
<description>Analog Comparator Flag Falling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFR</name>
<description>Analog Comparator Flag Rising</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEF</name>
<description>Comparator Interrupt Enable Falling</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IER</name>
<description>Comparator Interrupt Enable Rising</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACCR</name>
<description>DAC Control Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VOSEL</name>
<description>DAC Output Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRSEL</name>
<description>Supply Voltage Reference Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>V is selected as resistor ladder network supply reference V. in1 in</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>V is selected as resistor ladder network supply reference V. in2 in</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MUXCR</name>
<description>MUX Control Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Minus Input Mux Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSEL</name>
<description>Plus Input Mux Control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSTM</name>
<description>Pass Through Mode Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pass Through Mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pass Through Mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI0_</prependToName>
<baseAddress>0x40076000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>10</value>
</interrupt>
<registers>
<register>
<name>S</name>
<description>SPI Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODF</name>
<description>Master Mode Fault Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No mode fault error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTEF</name>
<description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMF</name>
<description>SPI Match Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Value in the receive data buffer matches the value in the MH:ML registers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPRF</name>
<description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BR</name>
<description>SPI Baud Rate Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPR</name>
<description>SPI Baud Rate Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Baud rate divisor is 2.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Baud rate divisor is 4.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Baud rate divisor is 8.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Baud rate divisor is 16.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Baud rate divisor is 32.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Baud rate divisor is 64.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Baud rate divisor is 128.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Baud rate divisor is 256.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Baud rate divisor is 512.</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPPR</name>
<description>SPI Baud Rate Prescale Divisor</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Baud rate prescaler divisor is 1.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Baud rate prescaler divisor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Baud rate prescaler divisor is 3.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Baud rate prescaler divisor is 4.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Baud rate prescaler divisor is 5.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Baud rate prescaler divisor is 6.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Baud rate prescaler divisor is 7.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Baud rate prescaler divisor is 8.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>SPI Control Register 2</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPC0</name>
<description>SPI Pin Control 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPISWAI</name>
<description>SPI Stop in Wait Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI clocks continue to operate in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI clocks stop when the MCU enters Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDMAE</name>
<description>Receive DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIDIROE</name>
<description>Bidirectional Mode Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI I/O pin enabled as an output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODFEN</name>
<description>Master Mode-Fault Function Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDMAE</name>
<description>Transmit DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIMODE</name>
<description>SPI 8-bit or 16-bit mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>8-bit SPI shift register, match register, and buffers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>16-bit SPI shift register, match register, and buffers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMIE</name>
<description>SPI Match Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPMF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPMF is 1, requests a hardware interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>SPI Control Register 1</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LSBFE</name>
<description>LSB First (shifter direction)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI serial data transfers start with the most significant bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI serial data transfers start with the least significant bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSOE</name>
<description>Slave Select Output Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Active-high SPI clock (idles low)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Active-low SPI clock (idles high)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI module configured as a slave SPI device</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI module configured as a master SPI device</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTIE</name>
<description>SPI Transmit Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPTEF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPTEF is 1, hardware interrupt requested</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPE</name>
<description>SPI System Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI system inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI system enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIE</name>
<description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ML</name>
<description>SPI Match Register low</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MH</name>
<description>SPI match register high</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DL</name>
<description>SPI Data Register low</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DH</name>
<description>SPI data register high</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI1_</prependToName>
<baseAddress>0x40077000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>S</name>
<description>SPI Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RFIFOEF</name>
<description>SPI read FIFO empty flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read FIFO is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFULLF</name>
<description>Transmit FIFO full flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has less than 8 bytes</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has 8 bytes of data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF</name>
<description>Transmit FIFO nearly empty flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF</name>
<description>Receive FIFO nearly full flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODF</name>
<description>Master Mode Fault Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No mode fault error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTEF</name>
<description>SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMF</name>
<description>SPI Match Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Value in the receive data buffer does not match the value in the MH:ML registers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Value in the receive data buffer matches the value in the MH:ML registers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPRF</name>
<description>SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BR</name>
<description>SPI Baud Rate Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPR</name>
<description>SPI Baud Rate Divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Baud rate divisor is 2.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Baud rate divisor is 4.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Baud rate divisor is 8.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Baud rate divisor is 16.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Baud rate divisor is 32.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Baud rate divisor is 64.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Baud rate divisor is 128.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Baud rate divisor is 256.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Baud rate divisor is 512.</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPPR</name>
<description>SPI Baud Rate Prescale Divisor</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Baud rate prescaler divisor is 1.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Baud rate prescaler divisor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Baud rate prescaler divisor is 3.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Baud rate prescaler divisor is 4.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Baud rate prescaler divisor is 5.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Baud rate prescaler divisor is 6.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Baud rate prescaler divisor is 7.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Baud rate prescaler divisor is 8.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>SPI Control Register 2</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPC0</name>
<description>SPI Pin Control 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPISWAI</name>
<description>SPI Stop in Wait Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI clocks continue to operate in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI clocks stop when the MCU enters Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDMAE</name>
<description>Receive DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for receive is disabled and interrupt from SPRF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for receive is enabled and interrupt from SPRF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIDIROE</name>
<description>Bidirectional Mode Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI I/O pin enabled as an output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODFEN</name>
<description>Master Mode-Fault Function Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDMAE</name>
<description>Transmit DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request for transmit is disabled and interrupt from SPTEF is allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request for transmit is enabled and interrupt from SPTEF is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIMODE</name>
<description>SPI 8-bit or 16-bit mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>8-bit SPI shift register, match register, and buffers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>16-bit SPI shift register, match register, and buffers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPMIE</name>
<description>SPI Match Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPMF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPMF is 1, requests a hardware interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>SPI Control Register 1</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LSBFE</name>
<description>LSB First (shifter direction)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI serial data transfers start with the most significant bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI serial data transfers start with the least significant bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSOE</name>
<description>Slave Select Output Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Active-high SPI clock (idles low)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Active-low SPI clock (idles high)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI module configured as a slave SPI device</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI module configured as a master SPI device</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPTIE</name>
<description>SPI Transmit Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPTEF inhibited (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When SPTEF is 1, hardware interrupt requested</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPE</name>
<description>SPI System Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI system inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI system enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIE</name>
<description>SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ML</name>
<description>SPI Match Register low</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MH</name>
<description>SPI match register high</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Hardware compare value (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DL</name>
<description>SPI Data Register low</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (low byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DH</name>
<description>SPI data register high</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>Bits</name>
<description>Data (high byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CI</name>
<description>SPI clear interrupt register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SPRFCI</name>
<description>Receive FIFO full flag clear interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SPTEFCI</name>
<description>Transmit FIFO empty flag clear interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RNFULLFCI</name>
<description>Receive FIFO nearly full flag clear interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TNEAREFCI</name>
<description>Transmit FIFO nearly empty flag clear interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXFOF</name>
<description>Receive FIFO overflow flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFOF</name>
<description>Transmit FIFO overflow flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO overflow condition has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO overflow condition occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFERR</name>
<description>Receive FIFO error flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A receive FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFERR</name>
<description>Transmit FIFO error flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit FIFO error occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transmit FIFO error occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>SPI control register 3</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FIFOMODE</name>
<description>FIFO mode enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer mode disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data available in the receive data buffer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLIEN</name>
<description>Receive FIFO nearly full interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon RNFULLF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon RNFULLF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEARIEN</name>
<description>Transmit FIFO nearly empty interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt upon TNEAREF being set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupts upon TNEAREF being set</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTCLR</name>
<description>Interrupt clearing mechanism select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>These interrupts are cleared by writing the corresponding bits in the CI register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNFULLF_MARK</name>
<description>Receive FIFO nearly full watermark</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RNFULLF is set when the receive FIFO has 48 bits or more</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RNFULLF is set when the receive FIFO has 32 bits or more</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNEAREF_MARK</name>
<description>Transmit FIFO nearly empty watermark</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TNEAREF is set when the transmit FIFO has 16 bits or less</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TNEAREF is set when the transmit FIFO has 32 bits or less</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LLWU</name>
<description>Low leakage wakeup unit</description>
<prependToName>LLWU_</prependToName>
<baseAddress>0x4007C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LLWU</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>PE1</name>
<description>LLWU Pin Enable 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE0</name>
<description>Wakeup Pin Enable For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE1</name>
<description>Wakeup Pin Enable For LLWU_P1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE2</name>
<description>Wakeup Pin Enable For LLWU_P2</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE3</name>
<description>Wakeup Pin Enable For LLWU_P3</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE2</name>
<description>LLWU Pin Enable 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE4</name>
<description>Wakeup Pin Enable For LLWU_P4</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE5</name>
<description>Wakeup Pin Enable For LLWU_P5</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE6</name>
<description>Wakeup Pin Enable For LLWU_P6</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE7</name>
<description>Wakeup Pin Enable For LLWU_P7</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE3</name>
<description>LLWU Pin Enable 3 register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE8</name>
<description>Wakeup Pin Enable For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE9</name>
<description>Wakeup Pin Enable For LLWU_P9</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE10</name>
<description>Wakeup Pin Enable For LLWU_P10</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE11</name>
<description>Wakeup Pin Enable For LLWU_P11</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE4</name>
<description>LLWU Pin Enable 4 register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE12</name>
<description>Wakeup Pin Enable For LLWU_P12</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE13</name>
<description>Wakeup Pin Enable For LLWU_P13</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE14</name>
<description>Wakeup Pin Enable For LLWU_P14</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE15</name>
<description>Wakeup Pin Enable For LLWU_P15</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ME</name>
<description>LLWU Module Enable register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUME0</name>
<description>Wakeup Module Enable For Module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME1</name>
<description>Wakeup Module Enable for Module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME2</name>
<description>Wakeup Module Enable For Module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME3</name>
<description>Wakeup Module Enable For Module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME4</name>
<description>Wakeup Module Enable For Module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME5</name>
<description>Wakeup Module Enable For Module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME6</name>
<description>Wakeup Module Enable For Module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME7</name>
<description>Wakeup Module Enable For Module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F1</name>
<description>LLWU Flag 1 register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF0</name>
<description>Wakeup Flag For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF1</name>
<description>Wakeup Flag For LLWU_P1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF2</name>
<description>Wakeup Flag For LLWU_P2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF3</name>
<description>Wakeup Flag For LLWU_P3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P3 input was not a wake-up source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P3 input was a wake-up source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF4</name>
<description>Wakeup Flag For LLWU_P4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF5</name>
<description>Wakeup Flag For LLWU_P5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF6</name>
<description>Wakeup Flag For LLWU_P6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF7</name>
<description>Wakeup Flag For LLWU_P7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F2</name>
<description>LLWU Flag 2 register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF8</name>
<description>Wakeup Flag For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P8 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P8 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF9</name>
<description>Wakeup Flag For LLWU_P9</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P9 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P9 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF10</name>
<description>Wakeup Flag For LLWU_P10</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P10 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P10 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF11</name>
<description>Wakeup Flag For LLWU_P11</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P11 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P11 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF12</name>
<description>Wakeup Flag For LLWU_P12</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P12 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P12 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF13</name>
<description>Wakeup Flag For LLWU_P13</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P13 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P13 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF14</name>
<description>Wakeup Flag For LLWU_P14</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P14 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P14 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF15</name>
<description>Wakeup Flag For LLWU_P15</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P15 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P15 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F3</name>
<description>LLWU Flag 3 register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MWUF0</name>
<description>Wakeup flag For module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF1</name>
<description>Wakeup flag For module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF2</name>
<description>Wakeup flag For module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF3</name>
<description>Wakeup flag For module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 3 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 3 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF4</name>
<description>Wakeup flag For module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF5</name>
<description>Wakeup flag For module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF6</name>
<description>Wakeup flag For module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF7</name>
<description>Wakeup flag For module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT1</name>
<description>LLWU Pin Filter 1 register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 1 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 1 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT2</name>
<description>LLWU Pin Filter 2 register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 2 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 2 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMC</name>
<description>Power Management Controller</description>
<prependToName>PMC_</prependToName>
<baseAddress>0x4007D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LVD_LVW</name>
<value>6</value>
</interrupt>
<registers>
<register>
<name>LVDSC1</name>
<description>Low Voltage Detect Status And Control 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVDV</name>
<description>Low-Voltage Detect Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (V LVD = V LVDL )</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>High trip point selected (V LVD = V LVDH )</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDRE</name>
<description>Low-Voltage Detect Reset Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LVDF does not generate hardware resets</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force an MCU reset when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDIE</name>
<description>Low-Voltage Detect Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDACK</name>
<description>Low-Voltage Detect Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVDF</name>
<description>Low-Voltage Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LVDSC2</name>
<description>Low Voltage Detect Status And Control 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVWV</name>
<description>Low-Voltage Warning Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (VLVW = VLVW1)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mid 1 trip point selected (VLVW = VLVW2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mid 2 trip point selected (VLVW = VLVW3)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>High trip point selected (VLVW = VLVW4)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWIE</name>
<description>Low-Voltage Warning Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVWF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWACK</name>
<description>Low-Voltage Warning Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVWF</name>
<description>Low-Voltage Warning Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage warning event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage warning event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>REGSC</name>
<description>Regulator Status And Control register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BGBE</name>
<description>Bandgap Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap buffer not enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap buffer enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGONS</name>
<description>Regulator In Run Regulation Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Regulator is in stop regulation or in transition to/from it</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Regulator is in run regulation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKISO</name>
<description>Acknowledge Isolation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripherals and I/O pads are in normal run state.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Certain peripherals and I/O pads are in an isolated and latched state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BGEN</name>
<description>Bandgap Enable In VLPx Operation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SMC</name>
<description>System Mode Controller</description>
<prependToName>SMC_</prependToName>
<baseAddress>0x4007E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PMPROT</name>
<description>Power Mode Protection register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVLLS</name>
<description>Allow Very-Low-Leakage Stop Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Any VLLSx mode is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Any VLLSx mode is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALLS</name>
<description>Allow Low-Leakage Stop Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLS is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLS is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVLP</name>
<description>Allow Very-Low-Power Modes</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>VLPR, VLPW, and VLPS are not allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>VLPR, VLPW, and VLPS are allowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Power Mode Control register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>STOPM</name>
<description>Stop Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Normal Stop (STOP)</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Very-Low-Power Stop (VLPS)</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Low-Leakage Stop (LLS)</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Very-Low-Leakage Stop (VLLSx)</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Reseved</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPA</name>
<description>Stop Aborted</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The previous stop mode entry was successsful.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The previous stop mode entry was aborted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUNM</name>
<description>Run Mode Control</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Normal Run mode (RUN)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Very-Low-Power Run mode (VLPR)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STOPCTRL</name>
<description>Stop Control Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VLLSM</name>
<description>VLLS Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>VLLS0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>VLLS1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>VLLS3</description>
<value>#011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORPO</name>
<description>POR Power Option</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>POR detect circuit is enabled in VLLS0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>POR detect circuit is disabled in VLLS0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSTOPO</name>
<description>Partial Stop Option</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>STOP - Normal Stop mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMSTAT</name>
<description>Power Mode Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PMSTAT</name>
<description>When debug is enabled, the PMSTAT will not update to STOP or VLPS When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCM</name>
<description>Reset Control Module</description>
<prependToName>RCM_</prependToName>
<baseAddress>0x4007F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SRS0</name>
<description>System Reset Status Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x82</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WAKEUP</name>
<description>Low Leakage Wakeup Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LLWU module wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LLWU module wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVD</name>
<description>Low-Voltage Detect Reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LVD trip or POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LVD trip or POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOC</name>
<description>Loss-of-Clock Reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of external clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of external clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOL</name>
<description>Loss-of-Lock Reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of lock in the PLL</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of lock in the PLL</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDOG</name>
<description>Watchdog</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by watchdog timeout</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by watchdog timeout</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIN</name>
<description>External Reset Pin</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by external reset pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by external reset pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POR</name>
<description>Power-On Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRS1</name>
<description>System Reset Status Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCKUP</name>
<description>Core Lockup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by core LOCKUP event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by core LOCKUP event</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SW</name>
<description>Software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by software setting of SYSRESETREQ bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDM_AP</name>
<description>MDM-AP System Reset Request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by host debugger system setting of the System Reset Request bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SACKERR</name>
<description>Stop Mode Acknowledge Error Reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFC</name>
<description>Reset Pin Filter Control register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSRW</name>
<description>Reset Pin Filter Select in Run and Wait Modes</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>All filtering disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bus clock filter enabled for normal operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>LPO clock filter enabled for normal operation</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTFLTSS</name>
<description>Reset Pin Filter Select in Stop Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All filtering disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPO clock filter enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFW</name>
<description>Reset Pin Filter Width register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSEL</name>
<description>Reset Pin Filter Bus Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>Bus clock filter count is 1</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>Bus clock filter count is 2</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>Bus clock filter count is 3</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>Bus clock filter count is 4</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>Bus clock filter count is 5</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>Bus clock filter count is 6</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>Bus clock filter count is 7</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>Bus clock filter count is 8</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>Bus clock filter count is 9</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>Bus clock filter count is 10</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>Bus clock filter count is 11</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>Bus clock filter count is 12</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>Bus clock filter count is 13</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>Bus clock filter count is 14</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>Bus clock filter count is 15</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>Bus clock filter count is 16</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>Bus clock filter count is 17</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>Bus clock filter count is 18</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>Bus clock filter count is 19</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>Bus clock filter count is 20</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>Bus clock filter count is 21</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>Bus clock filter count is 22</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>Bus clock filter count is 23</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>Bus clock filter count is 24</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11000</name>
<description>Bus clock filter count is 25</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>11001</name>
<description>Bus clock filter count is 26</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>Bus clock filter count is 27</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>Bus clock filter count is 28</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11100</name>
<description>Bus clock filter count is 29</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>Bus clock filter count is 30</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>Bus clock filter count is 31</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Bus clock filter count is 32</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOA_</prependToName>
<baseAddress>0x400FF000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTA</name>
<value>30</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOB_</prependToName>
<baseAddress>0x400FF040</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOC</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOC_</prependToName>
<baseAddress>0x400FF080</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC_PORTD</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOD</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOD_</prependToName>
<baseAddress>0x400FF0C0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC_PORTD</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOE</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOE_</prependToName>
<baseAddress>0x400FF100</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MTB</name>
<description>Micro Trace Buffer</description>
<prependToName>MTB_</prependToName>
<baseAddress>0xF0000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>POSITION</name>
<description>MTB Position Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>WRAP</name>
<description>This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER[MASK] field in the MASTER Trace Control Register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POINTER</name>
<description>Trace Packet Address Pointer[28:0]</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASTER</name>
<description>MTB Master Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFE0</resetMask>
<fields>
<field>
<name>MASK</name>
<description>Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSTARTEN</name>
<description>Trace Start Input Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSTOPEN</name>
<description>Trace Stop Input Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SFRWPRIV</name>
<description>Special Function Register Write Privilege</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RAMPRIV</name>
<description>RAM Privilege</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HALTREQ</name>
<description>Halt Request</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EN</name>
<description>Main Trace Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLOW</name>
<description>MTB Flow Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x4</resetMask>
<fields>
<field>
<name>AUTOSTOP</name>
<description>If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AUTOHALT</name>
<description>If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[HALTREQ] is automatically set to 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WATERMARK</name>
<description>WATERMARK[28:0]</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BASE</name>
<description>MTB Base Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>BASEADDR</name>
<description>This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MODECTRL</name>
<description>Integration Mode Control Register</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MODECTRL</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TAGSET</name>
<description>Claim TAG Set Register</description>
<addressOffset>0xFA0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TAGSET</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TAGCLEAR</name>
<description>Claim TAG Clear Register</description>
<addressOffset>0xFA4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TAGCLEAR</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LOCKACCESS</name>
<description>Lock Access Register</description>
<addressOffset>0xFB0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCKACCESS</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LOCKSTAT</name>
<description>Lock Status Register</description>
<addressOffset>0xFB4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCKSTAT</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>AUTHSTAT</name>
<description>Authentication Status Register</description>
<addressOffset>0xFB8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BIT0</name>
<description>Connected to DBGEN.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT1</name>
<description>Hardwired to 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT2</name>
<description>Connected to NIDEN or DBGEN signal.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIT3</name>
<description>Hardwired to 1.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICEARCH</name>
<description>Device Architecture Register</description>
<addressOffset>0xFBC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x47700A31</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICEARCH</name>
<description>Hardwired to 0x4770_0A31.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICECFG</name>
<description>Device Configuration Register</description>
<addressOffset>0xFC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICECFG</name>
<description>Hardwired to 0x0000_0000.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICETYPID</name>
<description>Device Type Identifier Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x31</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICETYPID</name>
<description>Hardwired to 0x0000_0031.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MTBDWT</name>
<description>MTB data watchpoint and trace</description>
<prependToName>MTBDWT_</prependToName>
<baseAddress>0xF0001000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>MTB DWT Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x2F000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DWTCFGCTRL</name>
<description>DWT configuration controls</description>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUMCMP</name>
<description>Number of comparators</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>COMP%s</name>
<description>MTB_DWT Comparator Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMP</name>
<description>Reference value for comparison</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>MASK%s</name>
<description>MTB_DWT Comparator Mask Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASK</name>
<description>MASK</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FCT0</name>
<description>MTB_DWT Comparator Function Register 0</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNCTION</name>
<description>Function</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Instruction fetch.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Data operand read.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Data operand write.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Data operand (read + write).</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVMATCH</name>
<description>Data Value Match</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Perform address comparison.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Perform data value comparison.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVSIZE</name>
<description>Data Value Size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Byte.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Halfword.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Word.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATAVADDR0</name>
<description>Data Value Address 0</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MATCHED</name>
<description>Comparator match</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No match.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Match occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCT1</name>
<description>MTB_DWT Comparator Function Register 1</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNCTION</name>
<description>Function</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Instruction fetch.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Data operand read.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Data operand write.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Data operand (read + write).</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATCHED</name>
<description>Comparator match</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No match.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Match occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TBCTRL</name>
<description>MTB_DWT Trace Buffer Control Register</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ACOMP0</name>
<description>Action based on Comparator 0 match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACOMP1</name>
<description>Action based on Comparator 1 match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NUMCOMP</name>
<description>Number of Comparators</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICECFG</name>
<description>Device Configuration Register</description>
<addressOffset>0xFC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICECFG</name>
<description>Hardwired to 0x0000_0000.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICETYPID</name>
<description>Device Type Identifier Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICETYPID</name>
<description>Hardwired to 0x0000_0004.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ROM</name>
<description>System ROM</description>
<prependToName>ROM_</prependToName>
<baseAddress>0xF0002000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2</dimIndex>
<name>ENTRY%s</name>
<description>Entry</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>ENTRY</name>
<description>ENTRY</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TABLEMARK</name>
<description>End of Table Marker Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MARK</name>
<description>Hardwired to 0x0000_0000</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SYSACCESS</name>
<description>System Access Register</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSACCESS</name>
<description>Hardwired to 0x0000_0001</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
<name>PERIPHID%s</name>
<description>Peripheral ID Register</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PERIPHID</name>
<description>Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>COMPID%s</name>
<description>Component ID Register</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>COMPID</name>
<description>Component ID</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCM</name>
<description>Core Platform Miscellaneous Control Module</description>
<prependToName>MCM_</prependToName>
<baseAddress>0xF0003000</baseAddress>
<addressBlock>
<offset>0x8</offset>
<size>0x3C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PLASC</name>
<description>Crossbar Switch (AXBS) Slave Configuration</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0x7</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ASC</name>
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus slave connection to AXBS input port n is absent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus slave connection to AXBS input port n is present.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLAMC</name>
<description>Crossbar Switch (AXBS) Master Configuration</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0xD</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>AMC</name>
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus master connection to AXBS input port n is absent</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus master connection to AXBS input port n is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLACR</name>
<description>Platform Control Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ARB</name>
<description>Arbitration select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fixed-priority arbitration for the crossbar masters</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Round-robin arbitration for the crossbar masters</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFCC</name>
<description>Clear Flash Controller Cache</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DFCDA</name>
<description>Disable Flash Controller Data Caching</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller data caching</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller data caching.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCIC</name>
<description>Disable Flash Controller Instruction Caching</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller instruction caching.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller instruction caching.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCC</name>
<description>Disable Flash Controller Cache</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller cache.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller cache.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EFDS</name>
<description>Enable Flash Data Speculation</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable flash data speculation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable flash data speculation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFCS</name>
<description>Disable Flash Controller Speculation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable flash controller speculation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Disable flash controller speculation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ESFC</name>
<description>Enable Stalling Flash Controller</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable stalling flash controller when flash is busy.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable stalling flash controller when flash is busy.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CPO</name>
<description>Compute Operation Control Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPOREQ</name>
<description>Compute Operation Request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Request is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request Compute Operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOACK</name>
<description>Compute Operation Acknowledge</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compute operation entry has not completed or compute operation exit has completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compute operation entry has completed or compute operation exit has not completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOWOI</name>
<description>Compute Operation Wake-up on Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FGPIOA</name>
<description>General Purpose Input/Output</description>
<groupName>FGPIO</groupName>
<prependToName>FGPIOA_</prependToName>
<baseAddress>0xF8000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FGPIOB</name>
<description>General Purpose Input/Output</description>
<groupName>FGPIO</groupName>
<prependToName>FGPIOB_</prependToName>
<baseAddress>0xF8000040</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FGPIOC</name>
<description>General Purpose Input/Output</description>
<groupName>FGPIO</groupName>
<prependToName>FGPIOC_</prependToName>
<baseAddress>0xF8000080</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FGPIOD</name>
<description>General Purpose Input/Output</description>
<groupName>FGPIO</groupName>
<prependToName>FGPIOD_</prependToName>
<baseAddress>0xF80000C0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FGPIOE</name>
<description>General Purpose Input/Output</description>
<groupName>FGPIO</groupName>
<prependToName>FGPIOE_</prependToName>
<baseAddress>0xF8000100</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>