Type Definition mk66f18::usbphy::anactrl::R

type R = R<u32, ANACTRL>;

Reader of register ANACTRL

Methods

impl R

pub fn testclk_sel(&self) -> TESTCLK_SEL_R

Bit 0 - Test clock selection to analog test

pub fn pfd_clkgate(&self) -> PFD_CLKGATE_R

Bit 1 - This bit field controls clock gating (disabling) for the PFD pfd_clk output for power savings when the PFD is not used

pub fn pfd_clk_sel(&self) -> PFD_CLK_SEL_R

Bits 2:3 - This bit field for the PFD selects the frequency relationship between the local pfd_clk output and the exported USB1PFDCLK

pub fn pfd_frac(&self) -> PFD_FRAC_R

Bits 4:9 - PFD fractional divider setting used to select the pfd_clk output frequency

pub fn dev_pulldown(&self) -> DEV_PULLDOWN_R

Bit 10 - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins

pub fn emph_pulse_ctrl(&self) -> EMPH_PULSE_CTRL_R

Bits 11:12 - Controls pre-emphasis time duration for the High Speed TX drivers after each data transition when the USBPHY_ANACTRL[EMPH_EN] bit is set high to 1'b1

pub fn emph_en(&self) -> EMPH_EN_R

Bit 13 - Enables pre-emphasis for the High-Speed TX drivers

pub fn emph_cur_ctrl(&self) -> EMPH_CUR_CTRL_R

Bits 14:15 - Controls the amount of pre-emphasis current added for the High-Speed TX drivers after each data transition when the USBPHY_ANACTRL[EMPH_EN] bit is set high to 1'b1

pub fn pfd_stable(&self) -> PFD_STABLE_R

Bit 31 - PFD stable signal from the Phase Fractional Divider.