mimxrt595s/dmic0/channel/
dc_ctrl.rs

1#[doc = "Register `DC_CTRL` reader"]
2pub struct R(crate::R<DC_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DC_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DC_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DC_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DC_CTRL` writer"]
17pub struct W(crate::W<DC_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DC_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DC_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DC_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DCPOLE` reader - DC Block Filter"]
38pub type DCPOLE_R = crate::FieldReader<u8, DCPOLE_A>;
39#[doc = "DC Block Filter\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum DCPOLE_A {
43    #[doc = "0: Flat Response, no filter"]
44    FLAT_RESPONSE = 0,
45    #[doc = "1: 155 Hz"]
46    HZ_155 = 1,
47    #[doc = "2: 78 Hz"]
48    HZ_78 = 2,
49    #[doc = "3: 39 Hz"]
50    HZ_39 = 3,
51}
52impl From<DCPOLE_A> for u8 {
53    #[inline(always)]
54    fn from(variant: DCPOLE_A) -> Self {
55        variant as _
56    }
57}
58impl DCPOLE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> DCPOLE_A {
62        match self.bits {
63            0 => DCPOLE_A::FLAT_RESPONSE,
64            1 => DCPOLE_A::HZ_155,
65            2 => DCPOLE_A::HZ_78,
66            3 => DCPOLE_A::HZ_39,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `FLAT_RESPONSE`"]
71    #[inline(always)]
72    pub fn is_flat_response(&self) -> bool {
73        *self == DCPOLE_A::FLAT_RESPONSE
74    }
75    #[doc = "Checks if the value of the field is `HZ_155`"]
76    #[inline(always)]
77    pub fn is_hz_155(&self) -> bool {
78        *self == DCPOLE_A::HZ_155
79    }
80    #[doc = "Checks if the value of the field is `HZ_78`"]
81    #[inline(always)]
82    pub fn is_hz_78(&self) -> bool {
83        *self == DCPOLE_A::HZ_78
84    }
85    #[doc = "Checks if the value of the field is `HZ_39`"]
86    #[inline(always)]
87    pub fn is_hz_39(&self) -> bool {
88        *self == DCPOLE_A::HZ_39
89    }
90}
91#[doc = "Field `DCPOLE` writer - DC Block Filter"]
92pub type DCPOLE_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, DC_CTRL_SPEC, u8, DCPOLE_A, 2, O>;
94impl<'a, const O: u8> DCPOLE_W<'a, O> {
95    #[doc = "Flat Response, no filter"]
96    #[inline(always)]
97    pub fn flat_response(self) -> &'a mut W {
98        self.variant(DCPOLE_A::FLAT_RESPONSE)
99    }
100    #[doc = "155 Hz"]
101    #[inline(always)]
102    pub fn hz_155(self) -> &'a mut W {
103        self.variant(DCPOLE_A::HZ_155)
104    }
105    #[doc = "78 Hz"]
106    #[inline(always)]
107    pub fn hz_78(self) -> &'a mut W {
108        self.variant(DCPOLE_A::HZ_78)
109    }
110    #[doc = "39 Hz"]
111    #[inline(always)]
112    pub fn hz_39(self) -> &'a mut W {
113        self.variant(DCPOLE_A::HZ_39)
114    }
115}
116#[doc = "Field `DCGAIN` reader - DC Gain"]
117pub type DCGAIN_R = crate::FieldReader<u8, u8>;
118#[doc = "Field `DCGAIN` writer - DC Gain"]
119pub type DCGAIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_CTRL_SPEC, u8, u8, 4, O>;
120#[doc = "Field `SATURATEAT16BIT` reader - Saturate at 16 Bit"]
121pub type SATURATEAT16BIT_R = crate::BitReader<SATURATEAT16BIT_A>;
122#[doc = "Saturate at 16 Bit\n\nValue on reset: 0"]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum SATURATEAT16BIT_A {
125    #[doc = "0: Do not Saturate. Results roll over if out range and do not saturate."]
126    DO_NOT_SATURATE = 0,
127    #[doc = "1: Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow."]
128    SATURATE = 1,
129}
130impl From<SATURATEAT16BIT_A> for bool {
131    #[inline(always)]
132    fn from(variant: SATURATEAT16BIT_A) -> Self {
133        variant as u8 != 0
134    }
135}
136impl SATURATEAT16BIT_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub fn variant(&self) -> SATURATEAT16BIT_A {
140        match self.bits {
141            false => SATURATEAT16BIT_A::DO_NOT_SATURATE,
142            true => SATURATEAT16BIT_A::SATURATE,
143        }
144    }
145    #[doc = "Checks if the value of the field is `DO_NOT_SATURATE`"]
146    #[inline(always)]
147    pub fn is_do_not_saturate(&self) -> bool {
148        *self == SATURATEAT16BIT_A::DO_NOT_SATURATE
149    }
150    #[doc = "Checks if the value of the field is `SATURATE`"]
151    #[inline(always)]
152    pub fn is_saturate(&self) -> bool {
153        *self == SATURATEAT16BIT_A::SATURATE
154    }
155}
156#[doc = "Field `SATURATEAT16BIT` writer - Saturate at 16 Bit"]
157pub type SATURATEAT16BIT_W<'a, const O: u8> =
158    crate::BitWriter<'a, u32, DC_CTRL_SPEC, SATURATEAT16BIT_A, O>;
159impl<'a, const O: u8> SATURATEAT16BIT_W<'a, O> {
160    #[doc = "Do not Saturate. Results roll over if out range and do not saturate."]
161    #[inline(always)]
162    pub fn do_not_saturate(self) -> &'a mut W {
163        self.variant(SATURATEAT16BIT_A::DO_NOT_SATURATE)
164    }
165    #[doc = "Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow."]
166    #[inline(always)]
167    pub fn saturate(self) -> &'a mut W {
168        self.variant(SATURATEAT16BIT_A::SATURATE)
169    }
170}
171#[doc = "Field `SIGNEXTEND` reader - Sign Extend"]
172pub type SIGNEXTEND_R = crate::BitReader<SIGNEXTEND_A>;
173#[doc = "Sign Extend\n\nValue on reset: 0"]
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175pub enum SIGNEXTEND_A {
176    #[doc = "0: Disabled"]
177    DISABLE = 0,
178    #[doc = "1: Enabled"]
179    ENABLE = 1,
180}
181impl From<SIGNEXTEND_A> for bool {
182    #[inline(always)]
183    fn from(variant: SIGNEXTEND_A) -> Self {
184        variant as u8 != 0
185    }
186}
187impl SIGNEXTEND_R {
188    #[doc = "Get enumerated values variant"]
189    #[inline(always)]
190    pub fn variant(&self) -> SIGNEXTEND_A {
191        match self.bits {
192            false => SIGNEXTEND_A::DISABLE,
193            true => SIGNEXTEND_A::ENABLE,
194        }
195    }
196    #[doc = "Checks if the value of the field is `DISABLE`"]
197    #[inline(always)]
198    pub fn is_disable(&self) -> bool {
199        *self == SIGNEXTEND_A::DISABLE
200    }
201    #[doc = "Checks if the value of the field is `ENABLE`"]
202    #[inline(always)]
203    pub fn is_enable(&self) -> bool {
204        *self == SIGNEXTEND_A::ENABLE
205    }
206}
207#[doc = "Field `SIGNEXTEND` writer - Sign Extend"]
208pub type SIGNEXTEND_W<'a, const O: u8> = crate::BitWriter<'a, u32, DC_CTRL_SPEC, SIGNEXTEND_A, O>;
209impl<'a, const O: u8> SIGNEXTEND_W<'a, O> {
210    #[doc = "Disabled"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut W {
213        self.variant(SIGNEXTEND_A::DISABLE)
214    }
215    #[doc = "Enabled"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut W {
218        self.variant(SIGNEXTEND_A::ENABLE)
219    }
220}
221impl R {
222    #[doc = "Bits 0:1 - DC Block Filter"]
223    #[inline(always)]
224    pub fn dcpole(&self) -> DCPOLE_R {
225        DCPOLE_R::new((self.bits & 3) as u8)
226    }
227    #[doc = "Bits 4:7 - DC Gain"]
228    #[inline(always)]
229    pub fn dcgain(&self) -> DCGAIN_R {
230        DCGAIN_R::new(((self.bits >> 4) & 0x0f) as u8)
231    }
232    #[doc = "Bit 8 - Saturate at 16 Bit"]
233    #[inline(always)]
234    pub fn saturateat16bit(&self) -> SATURATEAT16BIT_R {
235        SATURATEAT16BIT_R::new(((self.bits >> 8) & 1) != 0)
236    }
237    #[doc = "Bit 9 - Sign Extend"]
238    #[inline(always)]
239    pub fn signextend(&self) -> SIGNEXTEND_R {
240        SIGNEXTEND_R::new(((self.bits >> 9) & 1) != 0)
241    }
242}
243impl W {
244    #[doc = "Bits 0:1 - DC Block Filter"]
245    #[inline(always)]
246    #[must_use]
247    pub fn dcpole(&mut self) -> DCPOLE_W<0> {
248        DCPOLE_W::new(self)
249    }
250    #[doc = "Bits 4:7 - DC Gain"]
251    #[inline(always)]
252    #[must_use]
253    pub fn dcgain(&mut self) -> DCGAIN_W<4> {
254        DCGAIN_W::new(self)
255    }
256    #[doc = "Bit 8 - Saturate at 16 Bit"]
257    #[inline(always)]
258    #[must_use]
259    pub fn saturateat16bit(&mut self) -> SATURATEAT16BIT_W<8> {
260        SATURATEAT16BIT_W::new(self)
261    }
262    #[doc = "Bit 9 - Sign Extend"]
263    #[inline(always)]
264    #[must_use]
265    pub fn signextend(&mut self) -> SIGNEXTEND_W<9> {
266        SIGNEXTEND_W::new(self)
267    }
268    #[doc = "Writes raw bits to the register."]
269    #[inline(always)]
270    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
271        self.0.bits(bits);
272        self
273    }
274}
275#[doc = "DC Filter Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc_ctrl](index.html) module"]
276pub struct DC_CTRL_SPEC;
277impl crate::RegisterSpec for DC_CTRL_SPEC {
278    type Ux = u32;
279}
280#[doc = "`read()` method returns [dc_ctrl::R](R) reader structure"]
281impl crate::Readable for DC_CTRL_SPEC {
282    type Reader = R;
283}
284#[doc = "`write(|w| ..)` method takes [dc_ctrl::W](W) writer structure"]
285impl crate::Writable for DC_CTRL_SPEC {
286    type Writer = W;
287    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
288    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
289}
290#[doc = "`reset()` method sets DC_CTRL to value 0"]
291impl crate::Resettable for DC_CTRL_SPEC {
292    const RESET_VALUE: Self::Ux = 0;
293}
mimxrt595s/dmic0/channel/dc_ctrl.rs

mimxrt595s/dmic0/channel/
dc_ctrl.rs
