Struct microvmi::api::registers::X86Registers [−][src]
#[repr(C)]pub struct X86Registers {}Show fields
pub rax: u64, pub rbx: u64, pub rcx: u64, pub rdx: u64, pub rsi: u64, pub rdi: u64, pub rsp: u64, pub rbp: u64, pub r8: u64, pub r9: u64, pub r10: u64, pub r11: u64, pub r12: u64, pub r13: u64, pub r14: u64, pub r15: u64, pub rip: u64, pub rflags: u64, pub cr0: u64, pub cr2: u64, pub cr3: u64, pub cr4: u64, pub sysenter_cs: u64, pub sysenter_esp: u64, pub sysenter_eip: u64, pub msr_efer: u64, pub msr_star: u64, pub msr_lstar: u64, pub efer: u64, pub apic_base: u64, pub cs: SegmentReg, pub ds: SegmentReg, pub es: SegmentReg, pub fs: SegmentReg, pub gs: SegmentReg, pub ss: SegmentReg, pub tr: SegmentReg, pub ldt: SegmentReg, pub idt: SystemTableReg, pub gdt: SystemTableReg,
Expand description
Represents all x86 registers on a specific VCPU
Fields
rax: u64
8 byte general purpose register.
rbx: u64
8 byte general purpose register.
rcx: u64
8 byte general purpose register.
rdx: u64
8 byte general purpose register.
rsi: u64
8 byte general purpose register.
rdi: u64
8 byte general purpose register.
rsp: u64
8 byte general purpose register.
rbp: u64
8 byte general purpose register.
r8: u64
8 byte general purpose register.
r9: u64
8 byte general purpose register.
r10: u64
8 byte general purpose register.
r11: u64
8 byte general purpose register.
r12: u64
8 byte general purpose register.
r13: u64
8 byte general purpose register.
r14: u64
8 byte general purpose register.
r15: u64
8 byte general purpose register.
rip: u64
8 byte general purpose register.
rflags: u64
8 byte general purpose register.
cr0: u64
Has various control flags that modify the basic operation of the processor.
cr2: u64
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register. CR2 register cannot be intercepted by the guest operating system.
cr3: u64
CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory entry.
cr4: u64
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions.
sysenter_cs: u64
Contains the 32-bit segment selector for the privilege level 0 code segment. Its index value is 0x174.
sysenter_esp: u64
Contains the 32-bit offset into the privilege level 0 code segment to the first instruction of the selected operating procedure or routine. Its index value is 0x175.
sysenter_eip: u64
Contains the 32-bit stack pointer for the privilege level 0 stack. Its index value is 0x176.
msr_efer: u64
Extended Feature Enable Register (EFER) allows enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. Its index value is 0xc0000080.
msr_star: u64
Used to set the handler for SYSCALL and /or SYSRET instructions used for system calls. Its index value is 0xc0000081.
msr_lstar: u64
Used to set the handler for SYSCALL and /or SYSRET instructions used for system calls. Its index value is 0xc0000082.
efer: u64
Extened Feature Enable Register
apic_base: u64
Advanced Programmable Interrupt Control Register
cs: SegmentReg
Code segment register
ds: SegmentReg
Data segment register
es: SegmentReg
Extra segment register, customizable by the programmer.
fs: SegmentReg
Points to TIB(Thread Information block) of a process.
gs: SegmentReg
Points to TLS(Thread Local Storage) of a process.
ss: SegmentReg
Stack Segment Register
tr: SegmentReg
Task Register
ldt: SegmentReg
Local descriptor table register
idt: SystemTableReg
gdt: SystemTableReg
Trait Implementations
Returns the “default value” for a type. Read more
Auto Trait Implementations
impl RefUnwindSafe for X86Registers
impl Send for X86Registers
impl Sync for X86Registers
impl Unpin for X86Registers
impl UnwindSafe for X86Registers