megatiny_hal/attiny412pac/cpuint/
lvl1vec.rs

1#[doc = "Register `LVL1VEC` reader"]
2pub struct R(crate::attiny412pac::R<LVL1VEC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::attiny412pac::R<LVL1VEC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::attiny412pac::R<LVL1VEC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::attiny412pac::R<LVL1VEC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LVL1VEC` writer"]
17pub struct W(crate::attiny412pac::W<LVL1VEC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::attiny412pac::W<LVL1VEC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::attiny412pac::W<LVL1VEC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::attiny412pac::W<LVL1VEC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LVL1VEC` reader - Interrupt Vector with High Priority"]
38pub type LVL1VEC_R = crate::attiny412pac::FieldReader<u8, u8>;
39#[doc = "Field `LVL1VEC` writer - Interrupt Vector with High Priority"]
40pub type LVL1VEC_W<'a, const O: u8> = crate::attiny412pac::FieldWriterSafe<'a, u8, LVL1VEC_SPEC, u8, u8, 8, O>;
41impl R {
42    #[doc = "Bits 0:7 - Interrupt Vector with High Priority"]
43    #[inline(always)]
44    pub fn lvl1vec(&self) -> LVL1VEC_R {
45        LVL1VEC_R::new(self.bits)
46    }
47}
48impl W {
49    #[doc = "Bits 0:7 - Interrupt Vector with High Priority"]
50    #[inline(always)]
51    pub fn lvl1vec(&mut self) -> LVL1VEC_W<0> {
52        LVL1VEC_W::new(self)
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub fn bits(&mut self, bits: u8) -> &mut Self {
57        unsafe { self.0.bits(bits) };
58        self
59    }
60}
61#[doc = "Interrupt Level 1 Priority Vector\n\nThis register you can [`read`](crate::attiny412pac::generic::Reg::read), [`write_with_zero`](crate::attiny412pac::generic::Reg::write_with_zero), [`reset`](crate::attiny412pac::generic::Reg::reset), [`write`](crate::attiny412pac::generic::Reg::write), [`modify`](crate::attiny412pac::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lvl1vec](index.html) module"]
62pub struct LVL1VEC_SPEC;
63impl crate::attiny412pac::RegisterSpec for LVL1VEC_SPEC {
64    type Ux = u8;
65}
66#[doc = "`read()` method returns [lvl1vec::R](R) reader structure"]
67impl crate::attiny412pac::Readable for LVL1VEC_SPEC {
68    type Reader = R;
69}
70#[doc = "`write(|w| ..)` method takes [lvl1vec::W](W) writer structure"]
71impl crate::attiny412pac::Writable for LVL1VEC_SPEC {
72    type Writer = W;
73}
74#[doc = "`reset()` method sets LVL1VEC to value 0"]
75impl crate::attiny412pac::Resettable for LVL1VEC_SPEC {
76    #[inline(always)]
77    fn reset_value() -> Self::Ux {
78        0
79    }
80}
megatiny_hal/attiny412pac/cpuint/lvl1vec.rs

megatiny_hal/attiny412pac/cpuint/
lvl1vec.rs
