Struct max116xx_10bit::Max116xx10BitCnvstEocExt[][src]

pub struct Max116xx10BitCnvstEocExt<SPI, CS, EOC, CNVST, CLOCKED, WAKEUP = WithoutWakeupDelay> { /* fields omitted */ }

Implementations

Set up the ADC depending on clock and reference configuration

Set up the Averaging register. This sets the AVGON, NAVG1, NAVG0, NSCAN1 and NSCAN0 bits accordingly

Implementations when using the internal clock where CNVST is held low for the duration of the conversion

TODO: Implement. Unfortunately, the test board used to verify this library did not have the CNVST connected, so I wouldn’t be able to test an implementation easily.

Implementations when using the internal clock where CNVST is only pulsed to start acquisition and conversion

TODO: Test. Unfortunately, the test board used to verify this library did not have the CNVST connected, so I wouldn’t be able to test an implementation easily.

The pulse needs to be at least 40ns. A pulse cycle value can be used to increase the width of the pulse

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