[−][src]Enum ls7366::ir::Target

pub enum Target {
    Mdr0,
    Mdr1,
    Dtr,
    Cntr,
    Otr,
    Str,
    None,
}

Variants

Mdr0

Primary configuration register. See Mdr0 for configurable fields.

Mdr1

Secondary configuration register. See Mdr1 for configurable fields.

Dtr

Input register that can be directly written to from MOSI, contents may be transfered to Cntr under program control or hardware index signal.

Cntr

Counter register, indirectly accessible via Dtr and Otr.

Otr

Output register readable directly from MISO, serves as dump site for instantaneous data from Cntr, allowing read without interfering with counting operations.

Str

Status register, see Str for readable fields.

None

Trait Implementations

impl Debug for Target[src]

impl Encodable for Target[src]

Auto Trait Implementations

impl RefUnwindSafe for Target

impl Send for Target

impl Sync for Target

impl Unpin for Target

impl UnwindSafe for Target

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.