Enum lpc845_pac::usart0::cfg::CLKPOL_A

pub enum CLKPOL_A {
    FALLING_EDGE,
    RISING_EDGE,
}

Selects the clock polarity and sampling edge of received data in synchronous mode.

Value on reset: 0

Variants

FALLING_EDGE

0: Falling edge. Un_RXD is sampled on the falling edge of SCLK.

RISING_EDGE

1: Rising edge. Un_RXD is sampled on the rising edge of SCLK.

Trait Implementations

impl Clone for CLKPOL_A

fn clone(&self) -> CLKPOL_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CLKPOL_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<CLKPOL_A> for bool

fn from(variant: CLKPOL_A) -> Self

Performs the conversion.

impl PartialEq<CLKPOL_A> for CLKPOL_A

fn eq(&self, other: &CLKPOL_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for CLKPOL_A

impl StructuralPartialEq for CLKPOL_A