Struct lpc845_pac::spi0::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub cfg: Reg<CFG_SPEC>,
    pub dly: Reg<DLY_SPEC>,
    pub stat: Reg<STAT_SPEC>,
    pub intenset: Reg<INTENSET_SPEC>,
    pub intenclr: Reg<INTENCLR_SPEC>,
    pub rxdat: Reg<RXDAT_SPEC>,
    pub txdatctl: Reg<TXDATCTL_SPEC>,
    pub txdat: Reg<TXDAT_SPEC>,
    pub txctl: Reg<TXCTL_SPEC>,
    pub div: Reg<DIV_SPEC>,
    pub intstat: Reg<INTSTAT_SPEC>,
}

Expand description

Register block

Fields

cfg: Reg<CFG_SPEC>

0x00 - SPI Configuration register

dly: Reg<DLY_SPEC>

0x04 - SPI Delay register

stat: Reg<STAT_SPEC>

0x08 - SPI Status. Some status flags can be cleared by writing a 1 to that bit position

intenset: Reg<INTENSET_SPEC>

0x0c - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

intenclr: Reg<INTENCLR_SPEC>

0x10 - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

rxdat: Reg<RXDAT_SPEC>

0x14 - SPI Receive Data

txdatctl: Reg<TXDATCTL_SPEC>

0x18 - SPI Transmit Data with Control

txdat: Reg<TXDAT_SPEC>

0x1c - SPI Transmit Data.

txctl: Reg<TXCTL_SPEC>

0x20 - SPI Transmit Control

div: Reg<DIV_SPEC>

0x24 - SPI clock Divider