Struct lpc845_pac::spi0::div::DIVVAL_R

pub struct DIVVAL_R(_);

Field DIVVAL reader - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

Methods from Deref<Target = FieldReader<u16, u16>>

pub fn bits(&self) -> U

Reads raw bits from field.

pub fn bit(&self) -> bool

Value of the field as raw bits.

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0).

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1).

Trait Implementations

impl Deref for DIVVAL_R

type Target = FieldReader<u16, u16>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.