Enum lpc845_pac::sct0::config::CLKMODE_A [−][src]
#[repr(u8)]
pub enum CLKMODE_A {
SYSTEM_CLOCK_MODE,
SAMPLED_SYSTEM_CLOCK_MODE,
SCT_INPUT_CLOCK_MODE,
ASYNCHRONOUS_MODE,
}Expand description
SCT clock mode
Value on reset: 0
Variants
0: System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
1: Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
2: SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
3: Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.