Struct lpc845_pac::ctimer0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub ir: Reg<IR_SPEC>,
    pub tcr: Reg<TCR_SPEC>,
    pub tc: Reg<TC_SPEC>,
    pub pr: Reg<PR_SPEC>,
    pub pc: Reg<PC_SPEC>,
    pub mcr: Reg<MCR_SPEC>,
    pub mr: [Reg<MR_SPEC>; 4],
    pub ccr: Reg<CCR_SPEC>,
    pub cr: [Reg<CR_SPEC>; 4],
    pub emr: Reg<EMR_SPEC>,
    pub ctcr: Reg<CTCR_SPEC>,
    pub pwmc: Reg<PWMC_SPEC>,
    pub msr: [Reg<MSR_SPEC>; 4],
    // some fields omitted
}

Register block

Fields

ir: Reg<IR_SPEC>

0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

tcr: Reg<TCR_SPEC>

0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

tc: Reg<TC_SPEC>

0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.

pr: Reg<PR_SPEC>

0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.

pc: Reg<PC_SPEC>

0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

mcr: Reg<MCR_SPEC>

0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

mr: [Reg<MR_SPEC>; 4]

0x18..0x28 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

ccr: Reg<CCR_SPEC>

0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

cr: [Reg<CR_SPEC>; 4]

0x2c..0x3c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.

emr: Reg<EMR_SPEC>

0x3c - External Match Register. The EMR controls the match function and the external match pins.

ctcr: Reg<CTCR_SPEC>

0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

pwmc: Reg<PWMC_SPEC>

0x74 - PWM Control Register. The PWMCON enables PWM mode for the external match pins.

msr: [Reg<MSR_SPEC>; 4]

0x78..0x88 - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.