Struct lpc845_pac::capt::poll_tcnt::RDELAY_R [−][src]
pub struct RDELAY_R(_);
Expand description
Field RDELAY
reader - If not 0, this is the number of divided FCLKs to hold in Step 0 ‘Reset’ state (draining capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the divided FCLK added to the ‘Reset’ state.
Methods from Deref<Target = FieldReader<u8, u8>>
Returns true
if the bit is clear (0).
Returns true
if the bit is set (1).