Struct lpc845_pac::capt::ctrl::FDIV_R [−][src]
pub struct FDIV_R(_);
Expand description
Field FDIV
reader - Functional clock divider, or 0 if no divide. The term “clocks” in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide.
Implementations
Checks if the value of the field is FDIV_10
Checks if the value of the field is FDIV_11
Checks if the value of the field is FDIV_12
Checks if the value of the field is FDIV_13
Checks if the value of the field is FDIV_14
Checks if the value of the field is FDIV_15
Methods from Deref<Target = FieldReader<u8, FDIV_A>>
Returns true
if the bit is clear (0).
Returns true
if the bit is set (1).