Struct lpc845_pac::adc0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub ctrl: Reg<CTRL_SPEC>,
    pub seq_ctrla: Reg<SEQ_CTRL_SPEC>,
    pub seq_ctrlb: Reg<SEQ_CTRL_SPEC>,
    pub seq_gdata: Reg<SEQ_GDAT_SPEC>,
    pub seq_gdatb: Reg<SEQ_GDAT_SPEC>,
    pub dat: [Reg<DAT_SPEC>; 12],
    pub thr0_low: Reg<THR0_LOW_SPEC>,
    pub thr1_low: Reg<THR1_LOW_SPEC>,
    pub thr0_high: Reg<THR0_HIGH_SPEC>,
    pub thr1_high: Reg<THR1_HIGH_SPEC>,
    pub chan_thrsel: Reg<CHAN_THRSEL_SPEC>,
    pub inten: Reg<INTEN_SPEC>,
    pub flags: Reg<FLAGS_SPEC>,
    pub trm: Reg<TRM_SPEC>,
    // some fields omitted
}

Register block

Fields

ctrl: Reg<CTRL_SPEC>

0x00 - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.

seq_ctrla: Reg<SEQ_CTRL_SPEC>

0x08 - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

seq_ctrlb: Reg<SEQ_CTRL_SPEC>

0x0c - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

seq_gdata: Reg<SEQ_GDAT_SPEC>

0x10 - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.

seq_gdatb: Reg<SEQ_GDAT_SPEC>

0x14 - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.

dat: [Reg<DAT_SPEC>; 12]

0x20..0x50 - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.

thr0_low: Reg<THR0_LOW_SPEC>

0x50 - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr1_low: Reg<THR1_LOW_SPEC>

0x54 - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

thr0_high: Reg<THR0_HIGH_SPEC>

0x58 - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr1_high: Reg<THR1_HIGH_SPEC>

0x5c - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

chan_thrsel: Reg<CHAN_THRSEL_SPEC>

0x60 - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel

inten: Reg<INTEN_SPEC>

0x64 - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

flags: Reg<FLAGS_SPEC>

0x68 - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).

trm: Reg<TRM_SPEC>

0x6c - ADC Startup register.